Information

Table 24. 16-bit ADC characteristics (V
REFH
= V
DDA
, V
REFL
= V
SSA
) (continued)
Symbol Description
Conditions
1
Min.
Typ.
2
Max. Unit Notes
f
ADACK
ADC
asynchronous
clock source
• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
1.2
3.0
2.4
4.4
2.4
4.0
5.2
6.2
3.9
7.3
6.1
9.5
MHz
MHz
MHz
MHz
t
ADACK
= 1/
f
ADACK
Sample Time See Reference Manual chapter for sample times
TUE Total unadjusted
error
• 12 bit modes
• <12 bit modes
—
—
±4
±1.4
±6.8
±2.1
LSB
4
5
DNL Differential non-
linearity
• 12 bit modes
• <12 bit modes
—
—
±0.7
±0.2
-1.1 to
+1.9
-0.3 to 0.5
LSB
4
5
INL Integral non-
linearity
• 12 bit modes
• <12 bit modes
—
—
±1.0
±0.5
-2.7 to
+1.9
-0.7 to
+0.5
LSB
4
5
E
FS
Full-scale error • 12 bit modes
• <12 bit modes
—
—
-4
-1.4
-5.4
-1.8
LSB
4
V
ADIN
=
V
DDA
5
E
Q
Quantization
error
• 16 bit modes
• ≤13 bit modes
—
—
-1 to 0
—
—
±0.5
LSB
4
ENOB Effective number
of bits
16 bit differential mode
• Avg=32
• Avg=4
16 bit single-ended mode
• Avg=32
• Avg=4
12.8
11.9
12.2
11.4
14.5
13.8
13.9
13.1
—
—
—
—
bits
bits
bits
bits
6
SINAD
Signal-to-noise
plus distortion
See ENOB
6.02 × ENOB + 1.76 dB
THD Total harmonic
distortion
16 bit differential mode
• Avg=32
16 bit single-ended mode
• Avg=32
—
—
–94
-85
—
—
dB
dB
7
Table continues on the next page...
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
38 Freescale Semiconductor, Inc.