Information

6.6.2 CMP and 6-bit DAC electrical specifications
Table 25. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
V
DD
Supply voltage 1.71 — 3.6 V
I
DDHS
Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA
I
DDLS
Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA
V
AIN
Analog input voltage V
SS
– 0.3 — V
DD
V
V
AIO
Analog input offset voltage — — 20 mV
V
H
Analog comparator hysteresis
1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
10
20
30
—
—
—
—
mV
mV
mV
mV
V
CMPOh
Output high V
DD
– 0.5 — — V
V
CMPOl
Output low — — 0.5 V
t
DHS
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20 50 200 ns
t
DLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80 250 600 ns
Analog comparator initialization delay
2
— — 40 μs
I
DAC6b
6-bit DAC current adder (enabled) — 7 — μA
INL 6-bit DAC integral non-linearity –0.5 — 0.5
LSB
3
DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to V
DD
-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = V
reference
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Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc. 41