Information

DS3 DS4
DS1
DS2
DS7
DS8
First data
Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 15. DSPI classic SPI timing — master mode
Table 33. Slave mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit
Operating voltage 2.7 3.6 V
Frequency of operation 12.5 MHz
DS9 DSPI_SCK input cycle time 4 x t
BUS
— ns
DS10 DSPI_SCK input high/low time (t
SCK
/2) − 2 (t
SCK
/2) + 2 ns
DS11 DSPI_SCK to DSPI_SOUT valid — 20 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns
DS15 DSPI_SS active to DSPI_SOUT driven — 14 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven — 14 ns
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 16. DSPI classic SPI timing — slave mode
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc. 47