Information

8 Pinout
8.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
48
LQFP
-QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
1 VDD VDD VDD
2 VSS VSS VSS
3 USB0_DP USB0_DP USB0_DP
4 USB0_DM USB0_DM USB0_DM
5 VOUT33 VOUT33 VOUT33
6 VREGIN VREGIN VREGIN
7 ADC0_DP0 ADC0_DP0 ADC0_DP0
8 ADC0_DM0 ADC0_DM0 ADC0_DM0
9 VDDA VDDA VDDA
10 VREFH VREFH VREFH
11 VREFL VREFL VREFL
12 VSSA VSSA VSSA
13 VREF_OUT/
CMP1_IN5/
CMP0_IN5
VREF_OUT/
CMP1_IN5/
CMP0_IN5
VREF_OUT/
CMP1_IN5/
CMP0_IN5
14 XTAL32 XTAL32 XTAL32
15 EXTAL32 EXTAL32 EXTAL32
16 VBAT VBAT VBAT
17 PTA0 JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1 PTA0 UART0_CTS_
b/
UART0_COL_b
FTM0_CH5 JTAG_TCLK/
SWD_CLK
EZP_CLK
18 PTA1 JTAG_TDI/
EZP_DI
TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
19 PTA2 JTAG_TDO/
TRACE_SWO/
EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/
TRACE_SWO
EZP_DO
20 PTA3 JTAG_TMS/
SWD_DIO
TSI0_CH4 PTA3 UART0_RTS_b FTM0_CH0 JTAG_TMS/
SWD_DIO
21 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
22 VDD VDD VDD
23 VSS VSS VSS
Pinout
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
56 Freescale Semiconductor, Inc.