Information

48
LQFP
-QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
24 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0
25 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 LPTMR0_ALT1
26 RESET_b RESET_b RESET_b
27 PTB0/
LLWU_P5
ADC0_SE8/
TSI0_CH0
ADC0_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 FTM1_QD_
PHA
28 PTB1 ADC0_SE9/
TSI0_CH6
ADC0_SE9/
TSI0_CH6
PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_
PHB
29 PTB2 ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
PTB2 I2C0_SCL UART0_RTS_b FTM0_FLT3
30 PTB3 ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
PTB3 I2C0_SDA UART0_CTS_
b/
UART0_COL_b
FTM0_FLT0
31 PTB16 TSI0_CH9 TSI0_CH9 PTB16 UART0_RX EWM_IN
32 PTB17 TSI0_CH10 TSI0_CH10 PTB17 UART0_TX EWM_OUT_b
33 PTC0 ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
PTC0 SPI0_PCS4 PDB0_EXTRG
34 PTC1/
LLWU_P6
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
SPI0_PCS3 UART1_RTS_b FTM0_CH0 I2S0_TXD0
35 PTC2 ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2 SPI0_PCS2 UART1_CTS_b FTM0_CH1 I2S0_TX_FS
36 PTC3/
LLWU_P7
CMP1_IN1 CMP1_IN1 PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2 I2S0_TX_BCLK
37 PTC4/
LLWU_P8
DISABLED PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX FTM0_CH3 CMP1_OUT
38 PTC5/
LLWU_P9
DISABLED PTC5/
LLWU_P9
SPI0_SCK LPTMR0_ALT2 I2S0_RXD0 CMP0_OUT
39 PTC6/
LLWU_P10
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
SPI0_SOUT PDB0_EXTRG I2S0_RX_BCLK I2S0_MCLK
40 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_
OUT
I2S0_RX_FS
41 PTD0/
LLWU_P12
DISABLED PTD0/
LLWU_P12
SPI0_PCS0 UART2_RTS_b
42 PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK UART2_CTS_b
43 PTD2/
LLWU_P13
DISABLED PTD2/
LLWU_P13
SPI0_SOUT UART2_RX
44 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX
45 PTD4/
LLWU_P14
DISABLED PTD4/
LLWU_P14
SPI0_PCS1 UART0_RTS_b FTM0_CH4 EWM_IN
46 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_
b/
UART0_COL_b
FTM0_CH5 EWM_OUT_b
47 PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX FTM0_CH6 FTM0_FLT0
48 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1
Pinout
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc. 57