Datasheet

• One trigger output for ADC hardware trigger and up to eight pre-trigger outputs for ADC trigger select per PDB
channel
• Trigger outputs can be enabled or disabled independently.
• One 16-bit delay register per pre-trigger output
• Optional bypass of the delay registers of the pre-trigger outputs
• Operation in One-Shot or Continuous modes
• Optional back-to-back mode operation, which enables the ADC conversions complete to trigger the next PDB
channel
• One programmable delay interrupt
• One sequence error interrupt
• One channel flag and one sequence error flag per pre-trigger
• DMA support
• Up to eight DAC interval triggers
• One interval trigger output per DAC
• One 16-bit delay interval register per DAC trigger output
• Optional bypass the delay interval trigger registers
• Optional external triggers
• Up to eight pulse outputs (pulse-out's)
• Pulse-out's can be enabled or disabled independently.
• Programmable pulse width
4.5.6.2 FlexTimers (FTM)
• Selectale FTM source clock
• Programmable prescaler
• 16-bit counter supporting free-running or initial/final value, and counting is up or up-down
• Input capture, output compare, and edge-aligned and center-aligned PWM modes
• Input capture and output compare modes
• Operation of FTM channels as pairs with equal outputs, pairs with complimentary outputs, or independent channels
with independent outputs
• Deadtime insertion is available for each complementary pair
• Generation of hardware triggers
• Software control of PWM outputs
• Up to 4 fault inputs for global fault control
• Configurable channel polarity
• Programmable interrupt on input capture, reference compare, overflowed counter, or detected fault condition
• Quadrature decoder with input filters, relative position counting, and interrupt on position count or capture of position
count on external event
• DMA support for FTM events
• Global time base mode shares single time base across multiple FTM instances
4.5.6.3 Programmable Interrupt Timers (PITs)
• Up to 4 general purpose interrupt timers
• Up to 4 interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• Clocked by system clock frequency
• DMA support
4.5.6.4 Low Power Timer
• Operation as timer or pulse counter
Timers
K20 Family Product Brief, Rev. 11, 08/2012
Freescale Semiconductor, Inc. 41