Datasheet

Table 10. Chip power modes (continued)
Chip mode Description Core mode Normal
recovery
method
VLPR (Very Low
Power Run)
On-chip voltage regulator is in a low power mode that supplies only
enough power to run the chip at a reduced frequency. Reduced
frequency Flash access mode (1 MHz); LVD off; internal oscillator
provides a low power 4 MHz source for the core, the bus and the
peripheral clocks.
Run Interrupt
VLPW (Very
Low Power
Wait) -via WFI
Same as VLPR but with the core in sleep mode to further reduce
power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip
voltage regulator is in a low power mode that supplies only enough
power to run the chip at a reduced frequency.
Sleep Interrupt
VLPS (Very Low
Power Stop)-via
WFI
Places chip in static state with LVD operation off. Lowest power mode
with ADC and pin interrupts functional. Peripheral clocks are stopped,
but LPTimer, RTC, CMP, DAC can be used. NVIC is disabled (FCLK =
OFF); AWIC is used to wake up from interrupt. On-chip voltage
regulator is in a low power mode that supplies only enough power to
run the chip at a reduced frequency. All SRAM is operating (content
retained and I/O states held).
Sleep Deep Interrupt
LLS (Low
Leakage Stop)
State retention power mode. Most peripherals are in state retention
mode (with clocks stopped), but LLWU, LPTimer, RTC, CMP, DAC can
be used. NVIC is disabled; LLWU is used to wake up.
NOTE: The LLWU interrupt must not be masked by the interrupt
controller to avoid a scenario where the system does not fully
exit stop mode on an LLS recovery.
All SRAM is operating (content retained and I/O states held).
Sleep Deep Wakeup
Interrupt
1
VLLS3 (Very
Low Leakage
Stop3)
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
used to wake up.
SRAM_U and SRAM_L remain powered on (content retained and I/O
states held).
Sleep Deep Wakeup Reset
2
VLLS2 (Very
Low Leakage
Stop2)
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
used to wake up.
SRAM_L is powered off. A portion of SRAM_U remains powered on
(content retained and I/O states held).
Sleep Deep Wakeup Reset
2
VLLS1 (Very
Low Leakage
Stop1)
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
used to wake up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and the 32-byte VBAT register file remain powered for
customer-critical data.
Sleep Deep Wakeup Reset
2
VLLS0 (Very
Low Leakage
Stop 0)
Most peripherals are disabled (with clocks stopped), but LLWU and
RTC can be used. NVIC is disabled; LLWU is used to wake up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and the 32-byte VBAT register file remain powered for
customer-critical data.
The POR detect circuit can be optionally powered off.
Sleep Deep Wakeup Reset
2
Table continues on the next page...
Power modes
K20 Family Product Brief, Rev. 11, 08/2012
Freescale Semiconductor, Inc. 47