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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 32-Bit 50 MHz I/O number 40

K20 Sub-Family Reference Manual

Supports: MK20DN32VLH5, MK20DX32VLH5, MK20DN64VLH5,

MK20DX64VLH5, MK20DN128VLH5, MK20DX128VLH5,

MK20DN32VMP5, MK20DX32VMP5, MK20DN64VMP5,

MK20DX64VMP5, MK20DN128VMP5, MK20DX128VMP5

Document Number: K20P64M50SF0RM

Rev. 2, Feb 2012

Summary of content (1227 pages)

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K20 Sub-Family Reference Manual Supports: MK20DN32VLH5, MK20DX32VLH5, MK20DN64VLH5, MK20DX64VLH5, MK20DN128VLH5, MK20DX128VLH5, MK20DN32VMP5, MK20DX32VMP5, MK20DN64VMP5, MK20DX64VMP5, MK20DN128VMP5, MK20DX128VMP5 Document Number: K20P64M50SF0RM Rev.
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K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 2 Freescale Semiconductor, Inc.
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Contents Section Number Title Page Chapter 1 About This Document 1.1 1.2 Overview.......................................................................................................................................................................45 1.1.1 Purpose.........................................................................................................................................................45 1.1.2 Audience......................................................................
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Section Number 3.2 3.3 3.4 3.5 Title Page Core modules................................................................................................................................................................59 3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................59 3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................61 3.
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Section Number 3.6 3.8 3.9 3.10 Page 3.5.3 SRAM Configuration...................................................................................................................................88 3.5.4 System Register File Configuration.............................................................................................................91 3.5.5 VBAT Register File Configuration..............................................................................................................91 3.
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Section Number 4.2 Page System memory map.....................................................................................................................................................131 4.2.1 4.3 Title Aliased bit-band regions..............................................................................................................................132 Flash Memory Map..............................................................................................................................
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Section Number Title Page Chapter 6 Reset and Boot 6.1 Introduction...................................................................................................................................................................153 6.2 Reset..............................................................................................................................................................................154 6.3 6.2.1 Power-on reset (POR)....................................................
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Section Number Title Page Chapter 9 Debug 9.1 Introduction...................................................................................................................................................................177 9.1.1 9.2 References....................................................................................................................................................179 The Debug Port..............................................................................................
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Section Number 10.2.4 10.3 10.4 Title Page Signal multiplexing constraints....................................................................................................................193 Pinout............................................................................................................................................................................193 10.3.1 K20 Signal Multiplexing and Pin Assignments................................................................................
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Section Number Title Page Chapter 12 System Integration Module (SIM) 12.1 Introduction...................................................................................................................................................................221 12.1.1 12.2 12.3 Features........................................................................................................................................................221 Memory map and register definition....................................
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Section Number 13.2 Title Page Reset memory map and register descriptions...............................................................................................................253 13.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................253 13.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................255 13.2.
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Section Number 15.3.3 Title Page Low-voltage warning (LVW) interrupt operation.......................................................................................282 15.4 I/O retention..................................................................................................................................................................283 15.5 Memory map and register descriptions...............................................................................................................
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Section Number Title Page Chapter 17 Miscellaneous Control Module (MCM) 17.1 Introduction...................................................................................................................................................................311 17.1.1 17.2 Features........................................................................................................................................................311 Memory Map/Register Descriptions.........................................
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Section Number Title Page 20.2 External signal description............................................................................................................................................323 20.3 Memory map/register definition...................................................................................................................................323 20.3.1 20.4 20.5 Channel Configuration register (DMAMUXx_CHCFGn)...................................................................
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Section Number Title Page 21.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................355 21.3.13 Interrupt Request Register (DMA_INT)......................................................................................................355 21.3.14 Error Register (DMA_ERR)........................................................................................................................357 21.3.
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Section Number 21.4.4 21.5 Title Page Performance.................................................................................................................................................379 Initialization/application information...........................................................................................................................383 21.5.1 eDMA initialization......................................................................................................................
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Section Number Title Page Chapter 23 Watchdog Timer (WDOG) 23.1 Introduction...................................................................................................................................................................407 23.2 Features.........................................................................................................................................................................407 23.3 Functional overview...................................................
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Section Number 23.7.12 23.8 23.9 Title Page Watchdog Prescaler register (WDOG_PRESC)..........................................................................................424 Watchdog operation with 8-bit access..........................................................................................................................424 23.8.1 General guideline.........................................................................................................................................
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Section Number 24.5 Title Page 24.4.5 MCG Fixed frequency clock .......................................................................................................................452 24.4.6 MCG PLL clock ..........................................................................................................................................453 24.4.7 MCG Auto TRIM (ATM)............................................................................................................................
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Section Number 26.1.2 26.2 Title Page Block Diagram.............................................................................................................................................479 RTC Signal Descriptions..............................................................................................................................................480 26.2.1 EXTAL32 — Oscillator Input.............................................................................................................
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Section Number Title Page Chapter 28 Flash Memory Module (FTFL) 28.1 Introduction...................................................................................................................................................................497 28.1.1 Features........................................................................................................................................................498 28.1.2 Block Diagram..................................................................
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Section Number Title Page Chapter 29 EzPort 29.1 29.2 29.3 Overview.......................................................................................................................................................................559 29.1.1 Introduction..................................................................................................................................................559 29.1.2 Features.................................................................................
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Section Number Title Page Chapter 31 Analog-to-Digital Converter (ADC) 31.1 31.2 31.3 Introduction...................................................................................................................................................................581 31.1.1 Features........................................................................................................................................................581 31.1.2 Block diagram...............................................
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Section Number 31.4 31.5 Page 31.3.18 ADC minus-side general calibration value register (ADCx_CLMD)..........................................................604 31.3.19 ADC minus-side general calibration value register (ADCx_CLMS)..........................................................604 31.3.20 ADC minus-side general calibration value register (ADCx_CLM4)...........................................................605 31.3.21 ADC minus-side general calibration value register (ADCx_CLM3)........
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Section Number Title Page 32.4 ANMUX key features...................................................................................................................................................635 32.5 CMP, DAC and ANMUX diagram...............................................................................................................................635 32.6 CMP block diagram........................................................................................................................
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Section Number 33.1.4 33.2 33.3 33.4 Title Page VREF Signal Descriptions...........................................................................................................................663 Memory Map and Register Definition..........................................................................................................................664 33.2.1 VREF Trim Register (VREF_TRM)............................................................................................................
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Section Number 34.4 34.5 Title Page Functional Description..................................................................................................................................................682 34.4.1 PDB Pre-trigger and Trigger Outputs..........................................................................................................682 34.4.2 PDB Trigger Input Source Selection........................................................................................................
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Section Number 35.4 Title Page 35.3.12 Initial State For Channels Output (FTMx_OUTINIT).................................................................................711 35.3.13 Output Mask (FTMx_OUTMASK).............................................................................................................712 35.3.14 Function For Linked Channels (FTMx_COMBINE)...................................................................................714 35.3.
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Section Number Title Page 35.4.13 Software output control................................................................................................................................784 35.4.14 Deadtime insertion.......................................................................................................................................786 35.4.15 Output mask...................................................................................................................................
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Section Number 36.4 36.5 Title Page 36.3.2 Timer Load Value Register (PIT_LDVALn)...............................................................................................823 36.3.3 Current Timer Value Register (PIT_CVALn).............................................................................................823 36.3.4 Timer Control Register (PIT_TCTRLn)......................................................................................................824 36.3.
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Section Number Title Page Chapter 38 Carrier Modulator Transmitter (CMT) 38.1 Introduction...................................................................................................................................................................839 38.2 Features.........................................................................................................................................................................839 38.3 Block diagram...........................................
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Section Number Title Page Chapter 39 Real Time Clock (RTC) 39.1 39.2 39.3 Introduction...................................................................................................................................................................865 39.1.1 Features........................................................................................................................................................865 39.1.2 Modes of operation......................................................
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Section Number Title Page Chapter 40 Universal Serial Bus OTG Controller (USBOTG) 40.1 40.2 Introduction...................................................................................................................................................................883 40.1.1 USB..............................................................................................................................................................883 40.1.2 USB On-The-Go.........................................
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Section Number Title Page 40.4.15 Address Register (USBx_ADDR)................................................................................................................908 40.4.16 BDT Page Register 1 (USBx_BDTPAGE1)................................................................................................909 40.4.17 Frame Number Register Low (USBx_FRMNUML)...................................................................................909 40.4.
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Section Number Title Page 41.3 Module signal descriptions...........................................................................................................................................928 41.4 Memory map/Register definition..................................................................................................................................929 41.5 41.4.1 Control register (USBDCD_CONTROL).........................................................................................
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Section Number 43.2 43.3 43.4 Title Page 43.1.3 DSPI Configurations....................................................................................................................................959 43.1.4 Modes of Operation.....................................................................................................................................960 DSPI signal descriptions.................................................................................................................
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Section Number 43.5 Title Page 43.4.7 Interrupts/DMA requests..............................................................................................................................998 43.4.8 Power saving features..................................................................................................................................1000 Initialization/application information................................................................................................................
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Section Number 44.4 44.5 Title Page Functional description...................................................................................................................................................1023 44.4.1 I2C protocol.................................................................................................................................................1023 44.4.2 10-bit address.........................................................................................................
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Section Number Title Page 45.3.11 UART Control Register 4 (UARTx_C4).....................................................................................................1067 45.3.12 UART Control Register 5 (UARTx_C5).....................................................................................................1068 45.3.13 UART Extended Data Register (UARTx_ED)............................................................................................1069 45.3.
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Section Number 45.4 Title Page 45.3.40 UART CEA709.1-B Interrupt Enable Register (UARTx_IE).....................................................................1091 45.3.41 UART CEA709.1-B WBASE (UARTx_WB).............................................................................................1092 45.3.42 UART CEA709.1-B Status Register (UARTx_S3).....................................................................................1092 45.3.43 UART CEA709.1-B Status Register (UARTx_S4)........
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Section Number Title Page 45.8.6 Match address registers................................................................................................................................1142 45.8.7 Modem feature.............................................................................................................................................1142 45.8.8 IrDA minimum pulse width......................................................................................................................
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Section Number 46.4 Title Page 46.3.17 SAI Receive FIFO Register (I2Sx_RFRn)...................................................................................................1166 46.3.18 SAI Receive Mask Register (I2Sx_RMR)...................................................................................................1167 46.3.19 SAI MCLK Control Register (I2Sx_MCR).................................................................................................1168 46.3.
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Section Number Title Page Chapter 48 Touch sense input (TSI) 48.1 Introduction...................................................................................................................................................................1187 48.2 Features.........................................................................................................................................................................1187 48.3 Overview..........................................................
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Section Number 48.9 Title Page TSI module initialization..............................................................................................................................................1212 48.9.1 Initialization Sequence.................................................................................................................................1213 Chapter 49 JTAG Controller (JTAGC) 49.1 49.2 49.3 49.4 49.5 Introduction...............................................................
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Chapter 1 About This Document 1.1 Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the Freescale K20 microcontroller. 1.1.2 Audience This document is primarily for system architects and software application developers who are using or considering using the K20 microcontroller in a system. 1.2 Conventions 1.2.1 Numbering systems The following suffixes identify different numbering systems: This suffix Identifies a b Binary number.
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Conventions 1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers. code Fixed-width type indicates text that must be typed exactly as shown.
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Chapter 2 Introduction 2.1 Overview This chapter provides an overview of the Kinetis portfolio and K20 family of products. It also presents high-level descriptions of the modules available on the devices covered by this document. 2.2 Kinetis Portfolio Kinetis is the most scalable portfolio of low power, mixed-signal ARM®Cortex™-M4 MCUs in the industry. Phase 1 of the portfolio consists of five MCU families with over 200 pin-, peripheral- and software-compatible devices.
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Kinetis Portfolio Family Program Flash Packages K70 Family 512KB-1MB 196-256pin K6x Family 256KB-1MB 100-256pin K50 Family 128-512KB 64-144pin K40 Family 64-512KB 64-144pin K30 Family 64-512KB 64-144pin K20 Family 32KB-1MB 32-144pin K10 Family 32KB-1MB 32-144pin Low power Mixed signal Encryption and Tamper Detect Key Features USB Segment LCD Operational & transimpedance amplifiers DDR Ethernet Graphic LCD Figure 2-1.
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Chapter 2 Introduction • • • • • • • Scalable memory footprints from 32 KB flash / 8 KB RAM to 1 MB flash / 128 KB RAM. Independent flash banks enable concurrent code execution and firmware updates • Optional 16 KB cache memory for optimizing bus bandwidth and flash execution performance. Offered on K10, K20, and K60 family devices with CPU performance of up to 150 MHz. • FlexMemory with up to 512 KB FlexNVM and up to 16 KB FlexRAM.
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K20 Family Introduction • Wide operating voltage range from 1.71 V to 3.6 V with flash programmable down to 1.71 V with fully functional flash and analog peripherals • Ambient operating temperature ranges from -40 °C to 105 °C 2.3 K20 Family Introduction The K20 MCU family is pin, peripheral and software compatible with the K10 MCU family and adds full and high-speed USB 2.0 On-The-Go with device charger detect capability.
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Chapter 2 Introduction Table 2-1.
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Module Functional Categories Table 2-2. Core modules (continued) Module Description NVIC The ARMv7-M exception model and nested-vectored interrupt controller (NVIC) implement a relocatable vector table supporting many external interrupts, a single non-maskable interrupt (NMI), and priority levels. The NVIC replaces shadow registers with equivalent system and simplified programmability. The NVIC contains the address of the function to execute for a particular handler.
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Chapter 2 Introduction Table 2-3. System modules (continued) Module Description Direct memory access (DMA) controller The DMA controller provides programmable channels with transfer control descriptors for data movement via dual-address transfers for 8-, 16-, 32- and 128bit data values. External watchdog monitor (EWM) The EWM is a redundant mechanism to the software watchdog module that monitors both internal and external system operation for fail conditions.
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Module Functional Categories Table 2-5.
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Chapter 2 Introduction 2.4.7 Timer modules The following timer modules are available on this device: Table 2-8.
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Module Functional Categories Table 2-8.
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Chapter 2 Introduction Table 2-10. HMI modules Module Description General purpose input/output (GPIO) All general purpose input or output (GPIO) pins are capable of interrupt and DMA request generation. All GPIO pins have 5 V tolerance. Capacitive touch sense input (TSI) Contains up to 16 channel inputs for capacitive touch sensing applications. Operation is available in low-power modes via interrupts. 2.
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Orderable part numbers K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 58 Freescale Semiconductor, Inc.
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Chapter 3 Chip Configuration 3.1 Introduction This chapter provides details on the individual modules of the microcontroller. It includes: • module block diagrams showing immediate connections within the device, • specific module-to-module interactions not necessarily discussed in the individual module chapters, and • links for more information. 3.2 Core modules 3.2.1 ARM Cortex-M4 Core Configuration This section summarizes how the module has been configured in the chip.
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Core modules Interrupts PPB ARM Cortex-M4 Core Crossbar switch PPB Modules Debug Figure 3-1. Core configuration Table 3-1. Reference links to related information Topic Related module Reference Full description ARM Cortex-M4 core, r0p1 http://www.arm.com System memory map System memory map Clocking Clock distribution Power management Power management System/instruction/data bus module Crossbar switch Crossbar switch Debug IEEE 1149.
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Chapter 3 Chip Configuration 3.2.1.2 System Tick Timer The System Tick Timer's clock source is always the core clock, FCLK. This results in the following: • The CLKSOURCE bit in SysTick Control and Status register is always set to select the core clock. • Because the timing reference (FCLK) is a variable frequency, the TENMS bit in the SysTick Calibration Value Register is always zero.
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Core modules ARM Cortex-M4 core Interrupts Module Nested Vectored Interrupt Controller (NVIC) PPB Module Module Figure 3-2. NVIC configuration Table 3-2. Reference links to related information Topic Related module Reference Full description Nested Vectored Interrupt Controller (NVIC) http://www.arm.com System memory map System memory map Clocking Clock distribution Power management Power management Private Peripheral Bus (PPB) ARM Cortex-M4 core ARM Cortex-M4 core 3.2.2.
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Chapter 3 Chip Configuration • Vector number — the value stored on the stack when an interrupt is serviced. • IRQ number — non-core interrupt source count, which is the vector number minus 16. The IRQ number is used within ARM's NVIC documentation. Table 3-4.
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Core modules Table 3-4. Interrupt vector assignments (continued) Address IRQ1 Vector NVIC NVIC non-IPR IPR register register number number 2 0x0000_0064 25 9 0 Source module Source description 3 2 LLWU Low Leakage Wakeup NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery .
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Chapter 3 Chip Configuration Table 3-4.
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Core modules Table 3-5. LPTMR interrupt vector assignment Address Vector IRQ1 NVIC NVIC non-IPR IPR register register number number 2 0x0000_00DC 55 39 1 Source module Source description 3 9 Low Power Timer — 1. Indicates the NVIC's interrupt source number. 2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this value is: IRQ div 32 3. Indicates the NVIC's IPR register number used for this IRQ.
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Chapter 3 Chip Configuration Nested vectored interrupt controller (NVIC) Clock logic Wake-up requests Asynchronous Wake-up Interrupt Controller (AWIC) Module Module Figure 3-3. Asynchronous Wake-up Interrupt Controller configuration Table 3-6.
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System modules 3.2.4 JTAG Controller Configuration cJTAG Signal multiplexing This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. JTAG controller Figure 3-4. JTAGC Controller configuration Table 3-8. Reference links to related information Topic Related module Reference Full description JTAGC JTAGC Signal multiplexing Port control Signal multiplexing 3.3 System modules 3.3.
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Chapter 3 Chip Configuration Table 3-9. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock distribution Power management Power management 3.3.2 System Mode Controller (SMC) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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System modules Peripheral bridge Module signals Power Management Controller (PMC) Module signals System Mode Controller (SMC) Low-Leakage Wakeup Unit Register access Figure 3-7. PMC configuration Table 3-11.
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Chapter 3 Chip Configuration Peripheral bridge 0 Power Management Controller (PMC) Register access Wake-up requests Low-Leakage Wake-up Unit (LLWU) Module Module Figure 3-8. Low-Leakage Wake-up Unit configuration Table 3-12.
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System modules Table 3-13.
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Chapter 3 Chip Configuration Table 3-14. Reference links to related information (continued) Topic Related module Reference Transfers ARM Cortex-M4 core ARM Cortex-M4 core Private Peripheral Bus (PPB) 3.3.6 Crossbar-Light Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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System modules Table 3-15.
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Chapter 3 Chip Configuration 3.3.6.3 PRS register reset values The AXBS_PRSn registers reset to 0000_3210h. 3.3.7 Peripheral Bridge Configuration Transfers AIPS-Lite peripheral bridge Transfers Peripherals Crossbar switch This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Figure 3-11. Peripheral bridge configuration Table 3-16.
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System modules Peripheral bridge 0 Register access DMA controller Requests Channel request DMA Request Multiplexer Module Module Module Figure 3-12. DMA request multiplexer configuration Table 3-17.
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Chapter 3 Chip Configuration Table 3-18.
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System modules Table 3-18.
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Chapter 3 Chip Configuration Peripheral bridge 0 Transfers DMA Controller Requests DMA Multiplexer Crossbar switch Register access Figure 3-13. DMA Controller configuration Table 3-19.
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System modules Peripheral bridge 0 External Watchdog Monitor (EWM) Module signals Signal multiplexing Register access Figure 3-14. External Watchdog Monitor configuration Table 3-20. Reference links to related information Topic Related module Reference Full description External Watchdog Monitor (EWM) EWM System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port Control Module Signal multiplexing 3.3.10.
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Chapter 3 Chip Configuration 3.3.10.3 EWM_OUT pin state in low power modes During Wait, Stop and Power Down modes the EWM_OUT pin enters a high-impedance state. A user has the option to control the logic state of the pin using an external pull device or by configuring the internal pull device. When the CPU enters a Run mode from Wait or Stop recovery, the pin resumes its previous state before entering Wait or Stop mode. When the CPU enters Run mode from Power Down, the pin returns to its reset state. 3.3.
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Clock Modules Table 3-24. WDOG clock connections Module clock Chip clock LPO Oscillator 1 kHz LPO Clock Alt Clock Bus Clock Fast Test Clock Bus Clock System Bus Clock Bus Clock 3.3.11.2 WDOG low-power modes This table shows the WDOG low-power modes and the corresponding chip low-power modes. Table 3-25. WDOG low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS Power Down LLS, VLLSx 3.4 Clock Modules 3.4.
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Chapter 3 Chip Configuration Peripheral bridge System integration module (SIM) RTC System oscillator oscillator Register access Multipurpose Clock Generator (MCG) Figure 3-16. MCG configuration Table 3-26. Reference links to related information Topic Related module Reference Full description MCG MCG System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.4.
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Memories and Memory Interfaces Table 3-27. Reference links to related information (continued) Topic Related module Reference Power management Power management Signal multiplexing Port control Signal multiplexing Full description MCG MCG 3.4.2.1 OSC modes of operation with MCG The MCG's C2 register bits configure the oscillator frequency range. See the OSC and MCG chapters for more details. 3.4.
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Chapter 3 Chip Configuration Peripheral bus controller 0 Flash memory controller Register access Transfers Flash memory Figure 3-19. Flash memory configuration Table 3-29. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory System memory map System memory map Clocking Clock Distribution Transfers Flash memory controller Flash memory controller Register access Peripheral bridge Peripheral bridge 3.5.1.
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Memories and Memory Interfaces Device Program flash (KB) Block 0 (PFlash) address range FlexNVM (KB) FlexRAM (KB) FlexRAM address range MK20DN32VLH5 32 0x0000_0000 – 0x0001_FFFF — — — MK20DX32VLH5 32 0x0000_0000 – 0x0001_FFFF 32 2 0x1400_0000 – 0x1400_0FFF MK20DN64VLH5 64 0x0000_0000 – 0x0001_FFFF — — — MK20DX64VLH5 64 0x0000_0000 – 0x0001_FFFF 32 2 0x1400_0000 – 0x1400_0FFF MK20DN128VLH5 128 0x0000_0000 – 0x0001_FFFF — — — MK20DX128VLH5 128 0x0000_0000 – 0x0001_FFFF
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Chapter 3 Chip Configuration Flash memory base address Registers Program flash base address Flash configuration field Program flash FlexNVM base address FlexNVM FlexRAM base address FlexRAM Figure 3-20. Flash memory map 3.5.1.4 Flash Security How flash security is implemented on this device is described in Chip Security. 3.5.1.5 Flash Modes The flash memory operates in NVM normal and NVM special modes.
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Memories and Memory Interfaces 3.5.1.7 FTFL_FOPT Register The flash memory's FTFL_FOPT register allows the user to customize the operation of the MCU at boot time. See FOPT boot options for details of its definition. 3.5.2 Flash Memory Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration Cortex-M4 core crossbar SRAM controller SRAM upper Transfers switch SRAM controller SRAM lower Figure 3-22. SRAM configuration Table 3-31. Reference links to related information Topic Related module Reference Full description SRAM SRAM System memory map System memory map Clocking Clock Distribution Transfers SRAM controller SRAM controller ARM Cortex-M4 core ARM Cortex-M4 core 3.5.3.
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Memories and Memory Interfaces 3.5.3.2 SRAM Arrays The on-chip SRAM is split into two equally-sized logical arrays, SRAM_L and SRAM_U. The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. As such: • SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address. • SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning address.
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Chapter 3 Chip Configuration In VLLS1 and VLLS0 no SRAM is retained; however, the 32-byte register file is available. 3.5.4 System Register File Configuration This section summarizes how the module has been configured in the chip. Peripheral bridge 0 Register access Register file Figure 3-24. System Register file configuration Table 3-32.
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Memories and Memory Interfaces Peripheral bridge Register access VBAT register file Figure 3-25. VBAT Register file configuration Table 3-33. Reference links to related information Topic Related module Reference Full description VBAT register file VBAT register file System memory map System memory map Clocking Clock distribution Power management Power management 3.5.5.1 VBAT register file This device includes a 32-byte register file that is powered in all power modes and is powered by VBAT.
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Chapter 3 Chip Configuration Table 3-34. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing 3.5.6.1 JTAG instruction The system JTAG controller implements an EZPORT instruction.
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Analog Peripheral bridge Register access CRC Figure 3-27. CRC configuration Table 3-35. Reference links to related information Topic Related module Reference Full description CRC CRC System memory map System memory map Power management Power management 3.7 Analog 3.7.1 16-bit SAR ADC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration Table 3-36. Reference links to related information (continued) Topic Related module Reference Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.1.1 ADC instantiation information This device contains one ADC. 3.7.1.1.1 Number of ADC channels The number of ADC channels present on the device is determined by the pinout of the specific device package.
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Connections/Channel Assignment 3.7.1.3.1.
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Chapter 3 Chip Configuration 2. This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification. 3.7.1.4 ADC Channels MUX Selection The following figure shows the assignment of ADCx_SEn channels a and b through a MUX selection to ADC.
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Connections/Channel Assignment For operation of triggers in different modes, refer to Power Management chapter. 3.7.1.7 Alternate clock For this device, the alternate clock is connected to OSCERCLK. NOTE This clock option is only usable when OSCERCLK is in the MHz range. A system with OSCERCLK in the kHz range has the optional clock source below minimum ADC clock operating frequency. 3.7.1.8 ADC low-power modes This table shows the ADC low-power modes and the corresponding chip low-power modes.
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Chapter 3 Chip Configuration Peripheral bridge 0 CMP Other peripherals Module signals Signal multiplexing Register access Figure 3-30. CMP configuration Table 3-38. Reference links to related information Topic Related module Reference Full description Comparator (CMP) Comparator System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.2.
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Connections/Channel Assignment • VREF_OUT - Vin1 input • VDD - Vin2 input 3.7.2.3 External window/sample input Individual PDB pulse-out signals control each CMP Sample/Window timing. 3.7.3 VREF Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bus controller 0 Transfers Other peripherals VREF Module signals Signal multiplexing Register access Figure 3-31.
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Chapter 3 Chip Configuration NOTE PMC_REGSC[BGEN] bit must be set if the VREF regulator is required to remain operating in VLPx modes. NOTE For either an internal or external reference if the VREF_OUT functionality is being used, VREF_OUT signal must be connected to an output load capacitor. Refer the device data sheet for more details. 3.8 Timers 3.8.1 PDB Configuration This section summarizes how the module has been configured in the chip.
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Timers 3.8.1.1.1 PDB Output Triggers Table 3-42. PDB output triggers Number of PDB channels for ADC trigger 1 Number of pre-triggers per PDB channel 2 Number of PulseOut 2 NOTE There is an additional channel 1 to inter-connect with FTM0. 3.8.1.1.2 PDB Input Trigger Connections Table 3-43.
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Chapter 3 Chip Configuration 3.8.1.
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Timers 3.8.1.5 Pulse-Out Enable Register Implementation The following table shows the comparison of pulse-out enable register at the module and chip level. Table 3-44. PDB pulse-out enable register Register Module implementation Chip implementation POnEN 7:0 - POEN 0 - POEN[0] for CMP0 31:8 - Reserved 1 - POEN[1] for CMP1 31:2 - Reserved 3.8.2 FlexTimer Configuration This section summarizes how the module has been configured in the chip.
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Chapter 3 Chip Configuration Table 3-46. FTM Instantiations FTM instance Number of channels Features/usage FTM0 8 3-phase motor + 2 general purpose or stepper motor FTM1 21 Quadrature decoder or general purpose 1. Only channels 0 and 1 are available. Compared with the FTM0 configuration, the FTM1 configuration adds the Quadrature decoder feature and reduces the number of channels. 3.8.2.
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Timers • FTM1 FAULT0 = FTM1_FLT0 pin or CMP0 output • FTM1 FAULT1 = CMP1 output 3.8.2.
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Chapter 3 Chip Configuration 3.8.2.9 FTM Global Time Base This chip provides the optional FTM global time base feature (see Global time base (GTB)). FTM0 provides the only source for the FTM global time base. The other FTM modules can share the time base as shown in the following figure: FTM1 CONF Register GTBEOUT = 0 GTBEEN = 1 FTM0 CONF Register GTBEOUT = 1 GTBEEN = 1 gtb_in FTM Counter gtb_in FTM Counter gtb_out Figure 3-35. FTM Global Time Base Configuration 3.8.2.
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Timers Peripheral bridge Register access Periodic interrupt timer Figure 3-36. PIT configuration Table 3-47. Reference links to related information Topic Related module Reference Full description PIT PIT System memory map System memory map Clocking Clock Distribution Power management Power management 3.8.3.1 PIT/DMA Periodic Trigger Assignments The PIT generates periodic trigger events to the DMA Mux as shown in the table below. Table 3-48.
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Chapter 3 Chip Configuration Peripheral bridge Module signals Low-power timer Signal multiplexing Register access Figure 3-37. LPT configuration Table 3-49. Reference links to related information Topic Related module Reference Full description Low-power timer Low-power timer System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.8.4.
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Timers 3.8.4.2 LPTMR pulse counter input options The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield. LPTMR_CSR[TPS] Pulse counter input number Chip input 00 0 CMP0 output 01 1 LPTMR_ALT1 pin 10 2 LPTMR_ALT2 pin 11 3 Reserved 3.8.5 CMT Configuration This section summarizes how the module has been configured in the chip.
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Chapter 3 Chip Configuration 3.8.5.2 IRO Drive Strength The IRO pad requires higher current drive than can be obtained from a single pad. For this device, the pin associated with the CMT_IRO signal is doubled bonded to two pads. The SOPT2[PTD7PAD] field in SIM module can be used to configure the pin associated with the CMT_IRO signal as a higher current output port pin. 3.8.6 RTC configuration This section summarizes how the module has been configured in the chip.
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Communication interfaces RTC_CR[CLKO] RTC 32kHz clock RTC_CLKOUT RTC 1Hz clock SIM_SOPT2[RTCCLKOUTSEL] Figure 3-40. RTC_CLKOUT generation 3.8.6.2 RTC_WAKEUP signal The RTC_WAKEUP pin is not supported on this device. 3.9 Communication interfaces 3.9.1 Universal Serial Bus (USB) FS Subsystem The USB FS subsystem includes these components: • Dual-role USB OTG-capable (On-The-Go) controller that supports a full-speed (FS) device or FS/LS host. The module complies with the USB 2.0 specification.
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Chapter 3 Chip Configuration 3.9.1.1 USB Wakeup When the USB detects that there is no activity on the USB bus for more than 3 ms, the INT_STAT[SLEEP] bit is set. This bit can cause an interrupt and software decides the appropriate action. Waking from a low power mode (except in LLS/VLLS mode where USB is not powered) occurs through an asynchronous interrupt triggered by activity on the USB bus. Setting the USBTRC0[USBRESMEN] bit enables this function. 3.9.1.
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Communication interfaces 3.9.1.2.2 Li-Ion battery power supply The chip can also be powered by a single Li-ion battery. In this case, VOUT33 is connected to VDD. The USB regulator must be enabled by default to power the MCU. When connected to a USB host, the input source of this regulator is switched to the USB bus supply from the Li-ion battery. To charge the battery, the MCU can configure the battery charger according to the charger detection information.
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Chapter 3 Chip Configuration VDD To PMC and Pads VOUT33 Cstab Chip TYPE A VBUS VREGIN D+ USB0_DP D- USB0_DM USB Regulator USB XCVR USB Controller Figure 3-44. USB regulator bus supply 3.9.1.3 USB power management The regulator should be put into STANDBY mode whenever the chip is in Stop mode. This can be done by setting the two control bits on SIM_SOPT1. 3.9.1.4 USB controller configuration This section summarizes how the module has been configured in the chip.
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Communication interfaces Table 3-52. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing NOTE When USB is not used in the application, it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating. 3.9.1.
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USB Voltage Regulator Module signals Signal multiplexing USB OTG Chapter 3 Chip Configuration Figure 3-47. USB Voltage Regulator configuration Table 3-54.
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Communication interfaces Table 3-55. Reference links to related information (continued) Topic Related module Clocking Signal Multiplexing Reference Clock Distribution Port control Signal Multiplexing 3.9.2.1 SPI Modules Configuration This device contains one SPI module. 3.9.2.2 SPI clocking The SPI module is clocked by the internal bus clock (the DSPI refers to it as system clock). The module has an internal divider, with a minimum divide is two.
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Chapter 3 Chip Configuration Table 3-57. SPI receive FIFO size SPI Module Receive FIFO size SPI0 4 3.9.2.6 Number of PCS signals The following table shows the number of peripheral chip select signals available per SPI module. Table 3-58. SPI PCS signals SPI Module PCS Signals SPI0 SPI_PCS[4:0] SPI1 Not available 3.9.2.7 SPI Operation in Low Power Modes In VLPR and VLPW modes the SPI is functional; however, the reduced system frequency also reduces the max frequency of operation for the SPI.
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Communication interfaces select assertion and presentation of data, and the system interrupt latency. 3.9.2.8 SPI Doze Mode The Doze mode for the SPI module is the same as the Wait and VLPW modes for the chip. 3.9.2.9 SPI Interrupts The SPI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request to the interrupt controller. When an SPI interrupt occurs, read the SPI_SR to determine the exact interrupt source. 3.9.2.
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Chapter 3 Chip Configuration Peripheral bridge I2 C Module signals Signal multiplexing Register access Figure 3-49. I2C configuration Table 3-60. Reference links to related information Topic Related module Reference Full description I2C I 2C System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.9.4 UART Configuration This section summarizes how the module has been configured in the chip.
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Communication interfaces Table 3-61. Reference links to related information (continued) Topic Related module Power management Signal Multiplexing Reference Power management Port control Signal Multiplexing 3.9.4.1 UART configuration information This device contains three UART modules. This section describes how each module is configured on this device. 1.
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Chapter 3 Chip Configuration Source UART 0 UART 1 UART 2 Transmit data empty x x x Transmit complete x x x Idle line x x x Receive data full x x x LIN break detect x x x RxD pin active edge x x x Initial character detect x — — The error interrupt combines the following interrupt sources: Source UART 0 UART 1 UART 2 Receiver overrun x x x Noise flag x x x Framing error x x x Parity error x x x Transmitter buffer overflow x x x Receiver buffer underflow
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Communication interfaces Peripheral bridge I2 S Module signals Signal multiplexing Register access Figure 3-51. I2S configuration Table 3-62. Reference links to related information Topic Related module Reference Full description I2S I2S System memory map System memory map Clocking Clock Distribution Power management Power management Signal multiplexing Port control Signal Multiplexing 3.9.5.1 Instantiation information This device contains one I2S module.
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Chapter 3 Chip Configuration 3.9.5.2.2 Bit Clock The I2S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can be generated internally from the audio master clock or supplied externally. The module also supports the option for synchronous operation between the receiver and transmitter or between two separate I2S/SAI peripherals. 3.9.5.2.3 Bus Clock The bus clock is used by the control registers and to generate synchronous interrupts and DMA requests. 3.9.5.2.
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Communication interfaces The following table shows the TCR2[MSEL] and RCR2[MSEL] field settings for this device. Table 3-64. I2S0 master clock settings TCR2[MSEL], RCR2[MSEL] Master Clock 00 Bus Clock 01 I2S0_MCLK 10 Not supported 11 Not supported 3.9.5.2.5 Clock gating and I2S/SAI initialization The clock to the I2S/SAI module can be gated using a bit in the SIM. To minimize power consumption, these bits are cleared after any reset, which disables the clock to the corresponding module.
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Chapter 3 Chip Configuration In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitter is disabled after completing the current transmit frame, and, if the Receiver Stop Enable (RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receive frame. Entry into Stop mode is prevented–not acknowledged–while waiting for the transmitter and receiver to be disabled at the end of the current frame. 3.9.5.3.
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Human-machine interfaces (HMI) Table 3-65. Reference links to related information (continued) Topic Related module Reference Transfers Crossbar switch Clock Distribution Signal Multiplexing Port control Signal Multiplexing 3.10.1.1 GPIO access protection The GPIO module does not have access protection because it is not connected to a peripheral bridge slot. 3.10.1.
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Chapter 3 Chip Configuration 3.10.2.1 Number of inputs This device includes one TSI module containing 16 inputs. In low-power modes, one selectable pin is active. 3.10.2.2 TSI module functionality in MCU operation modes Table 3-67.
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Human-machine interfaces (HMI) Table 3-68. TSI clock connections Module clock Chip clock BUSCLK Bus clock MCGIRCLK MCGIRCLK OSCERCLK OSCERCLK LPOCLK 1 kHz LPO clock VLPOSCCLK ERCLK32K 3.10.2.4 TSI Interrupts The TSI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request. When a TSI interrupt occurs, read the TSI status register to determine the exact interrupt source. 3.10.2.
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Chapter 4 Memory Map 4.1 Introduction This device contains various memories and memory-mapped peripherals which are located in one 32-bit contiguous memory space. This chapter describes the memory and peripheral locations within that memory space. 4.2 System memory map The following table shows the high-level device memory map. Table 4-1.
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System memory map Table 4-1.
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Chapter 4 Memory Map A 32-bit read in the alias region returns either: • a value of 0x0000_0000 to indicate the target bit is clear • a value of 0x0000_0001 to indicate the target bit is set Bit-band region 31 Alias bit-band region 31 0 32 MByte 1 MByte 0 Figure 4-1. Alias bit-band mapping NOTE Each bit in bit-band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit-band region. 4.
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SRAM memory map Flash memory base address Registers Program flash base address Flash configuration field Program flash FlexNVM base address FlexNVM FlexRAM base address FlexRAM Figure 4-2. Flash memory map 4.3.1 Alternate Non-Volatile IRC User Trim Description The following non-volatile locations (4 bytes) are reserved for custom IRC user trim supported by some development tools. An alternate IRC trim to the factory loaded trim can be stored at this location.
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Chapter 4 Memory Map 4.5 Peripheral bridge (AIPS-Lite) memory map The peripheral memory map is accessible via one slave port on the crossbar in the 0x4000_0000–0x4007_FFFF region. The device implements one peripheral bridge that defines a 512 KB address space. Modules that are disabled via their clock gate control bits in the SIM registers disable the associated AIPS slots. Access to any address within an unimplemented or disabled peripheral bridge slot results in a transfer error termination.
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Peripheral bridge (AIPS-Lite) memory map Table 4-2.
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Chapter 4 Memory Map Table 4-2.
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Peripheral bridge (AIPS-Lite) memory map Table 4-2.
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Chapter 4 Memory Map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number 0x4007_8000 120 — 0x4007_9000 121 — 0x4007_A000 122 — 0x4007_B000 123 — 0x4007_C000 124 Low-leakage wakeup unit (LLWU) 0x4007_D000 125 Power management controller (PMC) 0x4007_E000 126 System Mode controller (SMC) 0x4007_F000 127 Reset Control Module (RCM) 0x400F_F000 Module GPIO controller 4.
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Private Peripheral Bus (PPB) memory map K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 140 Freescale Semiconductor, Inc.
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Chapter 5 Clock Distribution 5.1 Introduction The MCG module controls which clock source is used to derive the system clocks. The clock generation logic divides the selected clock source into a variety of clock domains, including the clocks for the system bus masters, system bus slaves, and flash memory. The clock generation logic also implements module-specific clock gating to allow granular shutoff of modules. The primary clocks for the system are generated from the MCGOUTCLK clock.
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Clock definitions OSC MCG SIM Multiplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2 Dividers — MCG_Cx SIM_CLKDIVx Clock gates OSC_CR MCG_C1 SIM_SCGCx SIM MCG 4 MHz IRC MCGIRCLK CG 32 kHz IRC MCGFFCLK FLL Clock options for some peripherals (see note) OUTDIV1 CG Core / system clocks OUTDIV2 CG Bus clock OUTDIV4 CG Flash clock MCGOUTCLK PLL MCGFLLCLK MCGPLLCLK MCGPLLCLK/ MCGFLLCLK System oscillator EXTAL0 OSCCLK XTAL_CLK XTAL0 EXTAL32 XTAL32 OSC logic OSCERCLK CG OSC32KCLK
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Chapter 5 Clock Distribution Clock name Description System clock MCGOUTCLK divided by OUTDIV1 clocks the crossbar switch and bus masters directly connected to the crossbar. In addition, this clock is used for UART0 and UART1.
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Internal clocking requirements Table 5-1.
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Chapter 5 Clock Distribution 1. The core and system clock frequencies must be 50 MHz or slower. 2. The bus clock frequency must be programmed to 50 MHz or less and an integer divide of the core clock. 3. The flash clock frequency must be programmed to 25 MHz or less, less than or equal to the bus clock, and an integer divide of the core clock.
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Clock Gating 5.6 Clock Gating The clock to each module can be individually gated on and off using the SIM module's SCGCx registers. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing a module, set the corresponding bit in SCGCx register to enable the clock. Before turning off the clock, make sure to disable the module. Any bus access to a peripheral that has its clock disabled generates an error termination. 5.
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Chapter 5 Clock Distribution Table 5-2.
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Module clocks 5.7.1 PMC 1-kHz LPO clock The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all modes of operation, including all low power modes except VLLS0. This 1-kHz source is commonly referred to as LPO clock or 1-kHz LPO clock. 5.7.2 WDOG clocking The WDOG may be clocked from two clock sources as shown in the following figure. LPO WDOG clock Bus clock WDOG_STCTRLH[CLKSRC] Figure 5-2. WDOG clock generation 5.7.
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Chapter 5 Clock Distribution NOTE The trace clock frequency observed at the TRACE_CLKOUT pin will be half that of the selected clock source. 5.7.4 PORT digital filter clocking The digital filters in each of the PORTx modules can be clocked as shown in the following figure. NOTE In stop mode, the digital input filters are bypassed unless they are configured to run from the 1 kHz LPO clock source. Bus clock PORTx digital input filter clock LPO PORTx_DFCR[CS] Figure 5-4.
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Module clocks MCGIRCLK LPO LPTMRx prescaler/glitch filter clock ERCLK32K OSCERCLK LPTMRx_PSR[PCS] Figure 5-5. LPTMRx prescaler/glitch filter clock generation 5.7.6 USB FS OTG Controller clocking The USB FS OTG controller is a bus master attached to the crossbar switch. As such, its clock is connected to the system clock. NOTE For the USB FS OTG controller to operate, the minimum system clock frequency is 20 MHz. The USB OTG controller also requires a 48 MHz clock.
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Chapter 5 Clock Distribution 5.7.7 UART clocking UART0 and UART1 modules operate from the core/system clock, which provides higher performance level for these modules. All other UART modules operate from the bus clock. 5.7.8 I2S/SAI clocking The audio master clock (MCLK) is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. The audio master clock can also be output to or input from a pin.
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Module clocks Bus clock TSI clock in active mode MCGIRCLK OSCERCLK TSI_SCANC[AMCLKS] Figure 5-8. TSI clock generation In low-power mode, the TSI can be clocked as shown in the following figure. NOTE In the TSI chapter, these two clocks are referred to as LPOCLK and VLPOSCCLK. LPO TSI clock in low-power mode ERCLK32K TSI_GENCS[LPCLKS] Figure 5-9. TSI low-power clock generation K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 152 Freescale Semiconductor, Inc.
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Chapter 6 Reset and Boot 6.1 Introduction The following reset sources are supported in this MCU: Table 6-1.
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Reset 6.2 Reset This section discusses basic reset mechanisms and sources. Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information. 6.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (VPOR), the POR circuit causes a POR reset condition.
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Chapter 6 Reset and Boot Note that the nTRST signal is initially configured as disabled, however once configured to its JTAG functionality its associated input pin is configured as: • nTRST in PU 6.2.2.1 External pin reset (PIN) On this device, RESET is a dedicated pin. This pin is open drain and has an internal pullup device. Asserting RESET wakes the device from any mode. During a pin reset, the RCM's SRS0[PIN] bit is set. 6.2.2.1.
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Reset 6.2.2.2 Low-voltage detect (LVD) The chip includes a system for managing low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip voltage. The LVD system is always enabled in normal run, wait, or stop mode. The LVD system is disabled when entering VLPx, LLS, or VLLSx modes.
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Chapter 6 Reset and Boot 6.2.2.5 Multipurpose clock generator loss-of-clock (LOC) The MCG module supports an external reference clock. If the C6[CME] bit in the MCG module is set, the clock monitor is enabled. If the external reference falls below floc_low or floc_high, as controlled by the C2[RANGE] field in the MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate this reset source.
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Reset 6.2.2.9 Lockup reset (LOCKUP) The LOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked because of an unrecoverable exception following the activation of the processor’s built in system state protection hardware. The LOCKUP condition causes a system reset and also causes the RCM's SRS1[LOCKUP] bit to set. 6.2.2.10 EzPort reset The EzPort supports a system reset request via EzPort signaling.
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Chapter 6 Reset and Boot 6.2.3.2 POR Only The POR Only reset asserts on the POR reset source only. It resets the PMC and System Register File. The POR Only reset also causes all other reset types (except VBAT POR) to occur. 6.2.3.3 Chip POR not VLLS The Chip POR not VLLS reset asserts on POR and LVD reset sources. It resets parts of the SMC and SIM. It also resets the LPTMR.
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Reset 6.2.3.7 Chip Reset Chip Reset asserts on all reset sources and only negates after flash initialization has completed and the RESET pin has also negated. It resets the remaining modules (the modules not reset by other reset types). 6.2.4 Reset Pin For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash initialization has completed.
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Chapter 6 Reset and Boot 6.2.5.3 Resetting the Debug subsystem Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug modules. However, as explained below, using the CDBGRSTREQ bit does not reset all debug-related registers.
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Boot The device can be in single chip (default) or serial flash programming mode (EzPort). While in single chip mode the device can be in run or various low power modes mentioned in Power mode transitions. Table 6-2. Mode select decoding EzPort chip select (EZP_CS) Description 0 Serial flash programming mode (EzPort) 1 Single chip (default) 6.3.3 FOPT boot options The flash option register (FOPT) in flash memory module (FTFL) allows the user to customize the operation of the MCU at boot time.
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Chapter 6 Reset and Boot Table 6-3. Flash Option Register (FTFL_FOPT) Bit Definitions (continued) Bit Num 0 Field LPBOOT Value Definition 0 Low-power boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at reset exit for higher divide values that produce lower power consumption at reset exit.
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Boot 7. When the system exits reset, the processor sets up the stack, program counter (PC), and link register (LR). The processor reads the start SP (SP_main) from vector-table offset 0. The core reads the start PC from vector-table offset 4. LR is set to 0xFFFF_FFFF. The CPU begins execution at the PC location. EzPort mode is entered instead of the normal CPU execution if Ezport mode was latched during the sequence. 8. If FlexNVM is enabled, the flash controller continues to restore the FlexNVM data.
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Chapter 7 Power Management 7.1 Introduction This chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 Power modes The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed.
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Power modes Table 7-1. Chip power modes (continued) Chip mode Description Normal Wait via WFI Allows peripherals to function while the core is in sleep mode, reducing power. NVIC remains sensitive to interrupts; peripherals continue to be clocked. Normal Stop via WFI Places chip in static state. Lowest power mode that retains all registers while maintaining LVD protection. NVIC is disabled; AWIC is used to wake up from interrupt; peripheral clocks are stopped.
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Chapter 7 Power Management Table 7-1. Chip power modes (continued) Chip mode VLLS0 (Very Low Leakage Stop 0) Description Core mode Normal recovery method Most peripherals are disabled (with clocks stopped), but LLWU and RTC can be used. NVIC is disabled; LLWU is used to wake up. Sleep Deep Wakeup Reset2 Off Power-up Sequence All of SRAM_U and SRAM_L are powered off. The 32-byte system register file and the 32-byte VBAT register file remain powered for customer-critical data.
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Power mode transitions If the oscillator was configured to continue running during VLLSx modes, it must be reconfigured before the ACKISO bit is cleared. The oscillator configuration within the MCG is cleared after VLLSx recovery and the oscillator will stop when ACKISO is cleared unless the register is re-configured. 7.4 Power mode transitions The following figure shows the power mode transitions. Any reset always brings the chip back to the normal run state.
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Chapter 7 Power Management Any reset VLPW 4 5 1 VLPR Wait 3 Run 6 7 2 Stop VLPS 8 10 11 9 LLS VLLS 3, 2, 1, 0 Figure 7-1. Power mode state transition diagram 7.5 Power modes shutdown sequencing When entering stop or other low-power modes, the clocks are shut off in an orderly sequence to safely place the chip in the targeted low-power state. All low-power entry sequences are initiated by the core executing an WFI instruction.
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Module Operation in Low Power Modes • Shuts off Core Clock and System Clock to the ARM Cortex-M4 core immediately. • Polls stop acknowledge indications from the non-core crossbar masters (DMA), supporting peripherals (SPI, PIT) and the Flash Controller for indications that System Clocks, Bus Clock and/or Flash Clock need to be left enabled to complete a previously initiated operation, effectively stalling entry to the targeted low power mode.
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Chapter 7 Power Management Table 7-2.
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Module Operation in Low Power Modes Table 7-2.
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Chapter 7 Power Management 6. These components remain powered in BAT power mode. 7. Use an externally generated bit clock or an externally generated audio master clock (including EXTAL). 8. System OSC and LPO clock sources are not available in VLLS0 9. RTC_CLKOUT is not available. 10. CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLS or VLLSx only supports low speed external pin to pin or external pin to DAC compares.
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Clock Gating K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 174 Freescale Semiconductor, Inc.
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Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 Flash Security The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits. The MCU, in turn, confirms the security request and limits access to flash resources.
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Security Interactions with other Modules 8.3 Security Interactions with other Modules The flash security settings are used by the SoC to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules. 8.3.1 Security Interactions with EzPort When flash security is active the MCU can still boot in EzPort mode.
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Chapter 9 Debug 9.1 Introduction This device's debug is based on the ARM coresight architecture and is configured in each device to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. Four debug interfaces are supported: • • • • IEEE 1149.1 JTAG IEEE 1149.7 JTAG (cJTAG) Serial Wire Debug (SWD) ARM Real-Time Trace Interface(1-pin asynchronous mode only) The basic Cortex-M4 debug architecture is very flexible.
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Introduction INTNMI INTISR[239:0] SLEEPING Cortex-M4 Interrupts Sleep NVIC Core ETM Debug SLEEPDEEP Instr. Trigger Data TPIU AWIC Trace port (serial wire or multi-pin) MCM FPB DWT ITM Private Peripheral Bus (internal) ROM Table APB i/f I-code bus Bus Matrix SW/ JTAG SWJ-DP D-code bus Code bus System bus AHB-AP MDM-AP Figure 9-1. Cortex-M4 Debug Topology The following table presents a brief description of each one of the debug components. Table 9-1.
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Chapter 9 Debug Table 9-1. Debug Components Description (continued) Module FPB (Flash Patch and Breakpoints) Description The FPB implements hardware breakpoints and patches code and data from code space to system space. The FPB unit contains two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space.
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The Debug Port IR==BYPASSor IDCODE 4’b1111 or 4’b0000 jtag_updateinstr[3:0] A TDI nTRST TCK TMS TDO TRACESWO TDO TDI TDO TDI (1’b1 = 4-pin JTAG) (1’b0 = 2-pin cJTAG) To Test Resources CJTAG TDI TDO PEN TDO TDI nSYS_TDO nSYS_TDI nTRST 1’b1 SWCLKTCK TCK JTAGC nSYS_TRST TCK TMS_OUT TMS_OUT_OE SWDITMS nSYS_TCK nSYS_TMS AHB-AP JTAGir[3:0] TMS_IN IR==BYPASSor IDCODE JTAGNSW A DAP Bus 4’b1111 or 4’b1110 MDM-AP TMS SWDO SWDOEN SWDSEL JTAGSEL SWDITMS SWCLKTCK SWD/ JTAG SELECT Figure
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Chapter 9 Debug 2. Set the control level to 2 via zero-bit scans 3. Execute the Store Format (STFMT) command (00011) to set the scan format register to 1149.7 scan format 9.3 Debug Port Pin Descriptions The debug port pins default after POR to their JTAG functionality with the exception of JTAG_TRST_b and can be later reassigned to their alternate functionalities. In cJTAG and SWD modes JTAG_TDI and JTAG_TRST_b can be configured to alternate GPIO functions. Table 9-2.
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JTAG status and control registers 9.4.1 IR Codes Table 9-3.
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Chapter 9 Debug It is important to note that these DAP control and status registers are not memory mapped within the system memory map and are only accessible via the Debug Access Port (DAP) using JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below. Table 9-4.
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JTAG status and control registers 9.5.1 MDM-AP Control Register Table 9-5. MDM-AP Control register assignments Bit 0 Secure1 Name Flash Mass Erase in Progress Y Description Set to cause mass erase. Cleared by hardware after mass erase operation completes. When mass erase is disabled (via MEEN and SEC settings), the erase request does not occur and the Flash Mass Erase in Progress bit continues to assert until the next system reset. 1 Debug Disable N Set to disable debug.
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Chapter 9 Debug Table 9-5. MDM-AP Control register assignments (continued) Bit 7 Secure1 Name LLS, VLLSx Status Acknowledge N Description Set this bit to acknowledge the DAP LLS and VLLS Status bits have been read. This acknowledge automatically clears the status bits. This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger.
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JTAG status and control registers Table 9-6. MDM-AP Status register assignments (continued) Bit 6 Name Backdoor Access Key Enable Description Indicates if the MCU has the backdoor access key enabled. 0 Disabled 1 Enabled 7 LP Enabled Decode of LPLLSM control bits to indicate that VLPS, LLS, or VLLSx are the selected power mode the next time the ARM Core enters Deep Sleep.
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Chapter 9 Debug 9.6 Debug Resets The debug system receives the following sources of reset: • JTAG_TRST_b from an external signal. This signal is optional and may not be available in all packages. • Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the TCLK domain that allows the debugger to reset the debug logic. • TRST asserted via the cJTAG escape command.
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ITM 9.8 ITM The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets. There are four sources that can generate packets. If multiple sources generate packets at the same time, the ITM arbitrates the order in which packets are output. The four sources in decreasing order of priority are: 1.
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Chapter 9 Debug • It contains four comparators that you can configure as a hardware watchpoint, a PC sampler event trigger, or a data address sampler event trigger. The first comparator, DWT_COMP0, can also compare against the clock cycle counter, CYCCNT. The second comparator, DWT_COMP1, can also be used as a data comparator.
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Debug & Security NOTE When using cJTAG and entering LLS mode, the cJTAG controller must be reset on exit from LLS mode. Going into a VLLSx mode causes all the debug controls and settings to be reset. To give time to the debugger to sync up with the HW, the MDM-AP Control register can be configured hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation. 9.12.
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Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. The Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin. 10.
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Signal Multiplexing Integration Table 10-1. Reference links to related information (continued) Topic Related module Clocking Reference Clock Distribution Register access Peripheral bus controller Peripheral bridge 10.2.1 Port control and interrupt module features • Five 32-pin ports NOTE Not all pins are available on the device. See the following section for details. NOTE The digital filters are only available on Port D. • Each 32-pin port is assigned one interrupt.
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Chapter 10 Signal Multiplexing and Signal Descriptions 10.2.4 Signal multiplexing constraints 1. A given peripheral function must be assigned to a maximum of one package pin. Do not program the same function to more than one pin. 2. To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other. 10.3 Pinout 10.3.
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Pinout 64 64 32 MAP LQF QFN BGA P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort H2 18 — CMP1_IN3/ CMP1_IN3/ CMP1_IN3/ ADC0_SE2 ADC0_SE2 ADC0_SE2 3 3 3 H3 19 9 XTAL32 XTAL32 XTAL32 H4 20 10 EXTAL32 EXTAL32 EXTAL32 H5 21 11 VBAT VBAT VBAT D3 22 12 PTA0 JTAG_TCL TSI0_CH1 K/ SWD_CLK/ EZP_CLK PTA0 UART0_CT FTM0_CH5 S_b/ UART0_CO L_b JTAG_TCL EZP_CLK K/ SWD_CLK D4 23 13 PTA1 JTAG_TDI/ TSI0_CH2 EZP_DI PTA1 UART0_RX FTM0_CH6 JTAG_TDI E5 24 14 PT
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Chapter 10 Signal Multiplexing and Signal Descriptions 64 64 32 MAP LQF QFN BGA P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 D6 41 — PTB18 TSI0_CH11 TSI0_CH11 PTB18 I2S0_TX_B CLK C7 42 — PTB19 TSI0_CH12 TSI0_CH12 PTB19 I2S0_TX_F S D8 43 — PTC0 ADC0_SE1 ADC0_SE1 PTC0 4/ 4/ TSI0_CH13 TSI0_CH13 SPI0_PCS4 PDB0_EXT RG C6 44 22 PTC1/ LLWU_P6 ADC0_SE1 ADC0_SE1 PTC1/ 5/ 5/ LLWU_P6 TSI0_CH14 TSI0_CH14 SPI0_PCS3 UART1_RT FTM0_CH0 S_b I2S0_TXD0 B7 45 23 PTC2 ADC0_SE4 b/
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Pinout 64 64 32 MAP LQF QFN BGA P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 B2 63 31 PTD6/ ADC0_SE7 ADC0_SE7 PTD6/ SPI0_PCS3 UART0_RX FTM0_CH6 LLWU_P15 b b LLWU_P15 FTM0_FLT 0 A2 64 32 PTD7 FTM0_FLT 1 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 ALT7 EzPort 10.3.2 K20 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin.
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PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Chapter 10 Signal Multiplexing and Signal Descriptions PTB18 ADC0_DP0 9 40 PTB17 ADC0_DM0 10 39 PTB16 ADC0_DP3 11 38 PTB3 ADC0_DM3 12 37 PTB2 VDDA 13 36 PTB1 VREFH 14 35 PTB0/LLWU_P5 VREFL 15 34 RESET_b VSSA 16 33 PTA19 VREF_OUT/CMP1_IN5/CMP0_IN5
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Module Signal Description Tables A B 1 2 3 4 5 6 PTE0 PTD7 PTD4/ LLWU_P14 PTD1 PTC11/ LLWU_P11 PTC8 PTD3 PTC10 PTC9 PTC7 VSS VDD PTD6/ PTE1/ LLWU_P0 LLWU_P15 PTD2/ PTD0/ LLWU_P13 LLWU_P12 7 8 PTC6/ PTC5/ LLWU_P10 LLWU_P9 A PTC2 PTC4/ LLWU_P8 B PTC1/ LLWU_P6 PTB19 PTC3/ LLWU_P7 C C PTD5 D USB0_DM VREGIN PTA0 PTA1 PTA3 PTB18 PTB17 PTC0 D E USB0_DP VOUT33 VSS VDD PTA2 PTB16 PTB2 PTB3 E F ADC0_DM0 ADC0_DM3 VSSA VDDA PTA5 PTB1 PTB0/ LLWU_P5 RESET_b
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Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-3. SWD Signal Descriptions Chip signal name Module signal name Description I/O SWD_DIO JTAG_TMS/ SWD_DIO Serial Wire Data I/O SWD_CLK JTAG_TCLK/ SWD_CLK Serial Wire Clock I Table 10-4. TPIU Signal Descriptions Chip signal name Module signal name Description I/O TRACE_SWO JTAG_TDO/ TRACE_SWO Trace output data from the ARM CoreSight debug block over a single pin O 10.4.2 System Modules Table 10-5.
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Module Signal Description Tables 10.4.3 Clock Modules Table 10-7. OSC Signal Descriptions Chip signal name Module signal name EXTAL0 EXTAL XTAL0 XTAL Description I/O External clock/Oscillator input I Oscillator output O Table 10-8. RTC OSC Signal Descriptions Chip signal name Module signal name EXTAL32 EXTAL32 XTAL32 XTAL32 Description I/O 32.768 kHz oscillator input I 32.768 kHz oscillator output O 10.4.4 Memories and Memory Interfaces Table 10-9.
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Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-11. CMP 0 Signal Descriptions Chip signal name Module signal name Description I/O CMP0_IN[5:0] IN[5:0] Analog voltage inputs I CMP0_OUT CMPO Comparator output O Table 10-12. CMP 1 Signal Descriptions Chip signal name Module signal name Description I/O CMP1_IN[5:0] IN[5:0] Analog voltage inputs I CMP1_OUT CMPO Comparator output O Table 10-13.
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Module Signal Description Tables Table 10-16. SPI 0 Signal Descriptions (continued) Chip signal name Module signal name SPI0_PCS[3:1] PCS[3:1] Description I/O Master mode: Peripheral Chip Select 1 – 3 O Slave mode: Unused SPI0_PCS4 PCS4 Master mode: Peripheral Chip Select 4 O Slave mode: Unused SPI0_SIN SIN SPI0_SOUT SOUT SPI0_SCK SCK Serial Data In I Serial Data Out O Master mode: Serial Clock (output) I/O Slave mode: Serial Clock (input) Table 10-17.
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Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-20. UART 2 Signal Descriptions (continued) Chip signal name Module signal name Description I/O UART2_RTS RTS Request to send O UART2_TX TXD Transmit data O UART2_RX RXD Receive data I Table 10-21.
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Module Signal Description Tables K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 204 Freescale Semiconductor, Inc.
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Chapter 11 Port control and interrupts (PORT) 11.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 11.1.1 Overview The port control and interrupt (PORT) module provides support for port control, and external interrupt functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state. There is one instance of the PORT module for each port.
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External signal description • Individual slew rate field supporting fast and slow slew rates • Individual input passive filter field supporting enable and disable of the individual input passive filter • Individual open drain field supporting enable and disable of the individual open drain output • Individual mux control field supporting analog or pin disabled, GPIO, and up to six chip-specific digital functions • Pad configuration fields are functional in all digital Pin Muxing modes 11.1.
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Chapter 11 Port control and interrupts (PORT) Table 11-1. Signal properties Name Function I/O Reset Pull PORTx[31:0] External interrupt I/O 0 - NOTE Not all pins within each port are implemented on each device. 11.3 Detailed signal description The following table contains the detailed signal description for the PORT interface. Table 11-2. PORT interface—detailed signal description Signal PORTx[31:0] I/O I/O Description External interrupt. State meaning Asserted—pin is logic one.
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Memory map and register definition PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_9018 Pin Control Register n (PORTA_PCR6) 32 R/W See section 11.4.1/213 4004_901C Pin Control Register n (PORTA_PCR7) 32 R/W See section 11.4.1/213 4004_9020 Pin Control Register n (PORTA_PCR8) 32 R/W See section 11.4.1/213 4004_9024 Pin Control Register n (PORTA_PCR9) 32 R/W See section 11.4.
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Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_A004 Pin Control Register n (PORTB_PCR1) 32 R/W See section 11.4.1/213 4004_A008 Pin Control Register n (PORTB_PCR2) 32 R/W See section 11.4.1/213 4004_A00C Pin Control Register n (PORTB_PCR3) 32 R/W See section 11.4.1/213 4004_A010 Pin Control Register n (PORTB_PCR4) 32 R/W See section 11.4.
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Memory map and register definition PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 0000_0000h 11.4.3/216 4004_A084 Global Pin Control High Register (PORTB_GPCHR) 32 W (always reads zero) 4004_A0A0 Interrupt Status Flag Register (PORTB_ISFR) 32 w1c 0000_0000h 11.4.4/217 4004_B000 Pin Control Register n (PORTC_PCR0) 32 R/W See section 11.4.1/213 4004_B004 Pin Control Register n (PORTC_PCR1) 32 R/W See section 11.4.
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Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_B078 Pin Control Register n (PORTC_PCR30) 32 R/W See section 11.4.1/213 4004_B07C Pin Control Register n (PORTC_PCR31) 32 R/W See section 11.4.1/213 32 W (always reads zero) 0000_0000h 11.4.2/216 0000_0000h 11.4.
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Memory map and register definition PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_C064 Pin Control Register n (PORTD_PCR25) 32 R/W See section 11.4.1/213 4004_C068 Pin Control Register n (PORTD_PCR26) 32 R/W See section 11.4.1/213 4004_C06C Pin Control Register n (PORTD_PCR27) 32 R/W See section 11.4.1/213 4004_C070 Pin Control Register n (PORTD_PCR28) 32 R/W See section 11.4.
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Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4004_D050 Pin Control Register n (PORTE_PCR20) 32 R/W See section 11.4.1/213 4004_D054 Pin Control Register n (PORTE_PCR21) 32 R/W See section 11.4.1/213 4004_D058 Pin Control Register n (PORTE_PCR22) 32 R/W See section 11.4.1/213 4004_D05C Pin Control Register n (PORTE_PCR23) 32 R/W See section 11.4.
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Memory map and register definition PORTx_PCRn field descriptions (continued) Field 24 ISF Description Interrupt Status Flag The pin interrupt configuration is valid in all digital pin muxing modes. 0 1 23–20 Reserved 19–16 IRQC Configured interrupt is not detected. Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
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Chapter 11 Port control and interrupts (PORT) PORTx_PCRn field descriptions (continued) Field 7 Reserved 6 DSE Description This read-only field is reserved and always has the value zero. Drive Strength Enable Drive strength configuration is valid in all digital pin muxing modes. 0 1 5 ODE Open Drain Enable Open drain configuration is valid in all digital pin muxing modes. 0 1 4 PFE 2 SRE Passive filter configuration is valid in all digital pin muxing modes.
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Memory map and register definition 11.4.2 Global Pin Control Low Register (PORTx_GPCLR) Only 32-bit writes are supported to this register.
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Chapter 11 Port control and interrupts (PORT) PORTx_GPCHR field descriptions Field Description 31–16 GPWE Global Pin Write Enable Selects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD. If a selected Pin Control Register is locked then the write to that register is ignored. 0 1 15–0 GPWD Corresponding Pin Control Register is not updated with the value in GPWD. Corresponding Pin Control Register is updated with the value in GPWD.
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Functional description 11.5 Functional description 11.5.1 Pin control Each port pin has a corresponding pin control register, PORT_PCRn, associated with it. The upper half of the pin control register configures the pin's capability to either interrupt the CPU or request a DMA transfer, on a rising/falling edge or both edges as well as a logic level occurring on the port pin. It also includes a flag to indicate that an interrupt has occurred.
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Chapter 11 Port control and interrupts (PORT) The global pin control registers are designed to enable software to quickly configure multiple pins within the one port for the same peripheral function. However, the interrupt functions cannot be configured using the global pin control registers. The global pin control registers are write-only registers, that always read as zero. 11.5.
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Functional description K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 220 Freescale Semiconductor, Inc.
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Chapter 12 System Integration Module (SIM) 12.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The system integration module (SIM) provides system control and chip configuration registers. 12.1.
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Memory map and register definition 12.2 Memory map and register definition The SIM module contains many bitfields for selecting the clock source and dividers for various module clocks. See the Clock Distribution chapter for more information including block diagrams and clock definitions. NOTE The SIM_SOPT1 and SIM_SOPT1CFG registers are located at a different base address than the other SIM registers.
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Chapter 12 System Integration Module (SIM) SIM memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4004_805C Unique Identification Register Mid Low (SIM_UIDML) 32 R See section 12.2.18/ 251 4004_8060 Unique Identification Register Low (SIM_UIDL) 32 R See section 12.2.19/ 251 20 19 12.2.1 System Options Register 1 (SIM_SOPT1) NOTE The SOPT1 register is only reset on POR or LVD.
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Memory map and register definition SIM_SOPT1 field descriptions (continued) Field Description 0 1 29 USBVSTBY USB voltage regulator in standby mode during VLPR and VLPW modes Controls whether the USB voltage regulator is placed in standby mode during VLPR and VLPW modes. 0 1 28–20 Reserved 19–18 OSC32KSEL USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
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Chapter 12 System Integration Module (SIM) 12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG) NOTE The SOPT1CFG register is reset on System Reset not VLLS.
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Memory map and register definition 12.2.3 System Options Register 2 (SIM_SOPT2) SOPT2 contains the controls for selecting many of the module clock source options on this device. See the Clock Distribution chapter for more information including clocking diagrams and definitions of device clocks.
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Chapter 12 System Integration Module (SIM) SIM_SOPT2 field descriptions Field Description 31–30 Reserved This read-only field is reserved and always has the value zero. 29–28 Reserved This read-only field is reserved and always has the value zero. 27–22 Reserved This read-only field is reserved and always has the value zero. 21–19 Reserved This read-only field is reserved and always has the value zero. 18 USBSRC USB clock source select Selects the clock source for the USB 48 MHz clock.
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Memory map and register definition SIM_SOPT2 field descriptions (continued) Field Description 011 100 101 110 111 LPO clock (1 kHz) MCGIRCLK RTC 32.768kHz clock OSCERCLK0 Reserved 4 RTC clock out select RTCCLKOUTSE Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the RTC_CLKOUT pin. L 0 1 3–0 Reserved RTC 1 Hz clock is output on the RTC_CLKOUT pin. RTC 32.768kHz clock is output on the RTC_CLKOUT pin. This read-only field is reserved and always has the value zero.
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Chapter 12 System Integration Module (SIM) 12.2.
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Memory map and register definition SIM_SOPT4 field descriptions (continued) Field Description 0 1 HSCMP0 output drives FTM0 hardware trigger 0 FTM1 channel match drives FTM0 hardware trigger 0 27 Reserved This read-only field is reserved and always has the value zero. 26 Reserved This read-only field is reserved and always has the value zero. 25 FTM1CLKSEL FTM1 External Clock Pin Select Selects the external pin used to drive the clock to the FTM1 module.
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Chapter 12 System Integration Module (SIM) SIM_SOPT4 field descriptions (continued) Field Description NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. 0 1 FTM1_FLT0 pin CMP0 out 3 Reserved This read-only field is reserved and always has the value zero. 2 Reserved This read-only field is reserved and always has the value zero.
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Memory map and register definition 12.2.
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Chapter 12 System Integration Module (SIM) SIM_SOPT5 field descriptions (continued) Field Description 01 10 11 1 Reserved 0 UART0TXSRC CMP0 CMP1 Reserved This read-only field is reserved and always has the value zero. UART 0 transmit data source select Selects the source for the UART 0 transmit data. 0 1 UART0_TX pin UART0_TX pin modulated with FTM1 channel 0 output K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 Freescale Semiconductor, Inc.
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Memory map and register definition 12.2.
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Chapter 12 System Integration Module (SIM) SIM_SOPT7 field descriptions (continued) Field Description 7 ADC0ALTTRGEN ADC0 alternate trigger enable Enable alternative conversion triggers for ADC0. 0 1 6–5 Reserved PDB trigger selected for ADC0. Alternate trigger selected for ADC0. This read-only field is reserved and always has the value zero. 4 ADC0 pretrigger select ADC0PRETRGSEL Selects the ADC0 pre-trigger source when alternative triggers are enabled through ADC0ALTTRGEN.
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Memory map and register definition SIM_SDID field descriptions Field 31–16 Reserved 15–12 REVID Description This read-only field is reserved and always has the value zero. Device revision number Specifies the silicon implementation number for the device. 11 Reserved This read-only field is reserved and always has the value zero. 10 Reserved This read-only field is reserved and always has the value zero. 9 Reserved This read-only field is reserved and always has the value zero.
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Chapter 12 System Integration Module (SIM) 12.2.
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Memory map and register definition SIM_SCGC4 field descriptions (continued) Field 12 UART2 Description UART2 Clock Gate Control This bit controls the clock gate to the UART2 module. 0 1 11 UART1 UART1 Clock Gate Control This bit controls the clock gate to the UART1 module. 0 1 10 UART0 Clock disabled Clock enabled Clock disabled Clock enabled UART0 Clock Gate Control This bit controls the clock gate to the UART0 module.
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Chapter 12 System Integration Module (SIM) 12.2.
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Memory map and register definition SIM_SCGC5 field descriptions (continued) Field Description 0 1 10 PORTB Port B Clock Gate Control This bit controls the clock gate to the Port B module. 0 1 9 PORTA Clock disabled Clock enabled Clock disabled Clock enabled Port A Clock Gate Control This bit controls the clock gate to the Port A module. 0 1 Clock disabled Clock enabled 8–7 Reserved This read-only field is reserved and always has the value one.
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Chapter 12 System Integration Module (SIM) 12.2.
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Memory map and register definition SIM_SCGC6 field descriptions (continued) Field 24 FTM0 Description FTM0 Clock Gate Control This bit controls the clock gate to the FTM0 module. 0 1 23 PIT PIT Clock Gate Control This bit controls the clock gate to the PIT module. 0 1 22 PDB This bit controls the clock gate to the PDB module. 18 CRC This bit controls the clock gate to the USB DCD module. 15 I2S Clock disabled Clock enabled This read-only field is reserved and always has the value zero.
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Chapter 12 System Integration Module (SIM) SIM_SCGC6 field descriptions (continued) Field Description 0 1 Clock disabled Clock enabled 11–10 Reserved This read-only field is reserved and always has the value zero. 9 Reserved This read-only field is reserved and always has the value zero. 8–5 Reserved This read-only field is reserved and always has the value zero. 4 Reserved This read-only field is reserved and always has the value zero.
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Memory map and register definition SIM_SCGC7 field descriptions (continued) Field Description This bit controls the clock gate to the DMA module. 0 1 0 Reserved Clock disabled Clock enabled This read-only field is reserved and always has the value zero. 12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1) NOTE The CLKDIV1 register cannot be written to when the device is in VLPR mode.
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Chapter 12 System Integration Module (SIM) SIM_CLKDIV1 field descriptions (continued) Field Description 1101 1110 1111 27–24 OUTDIV2 Divide-by-14. Divide-by-15. Divide-by-16. Clock 2 output divider value This field sets the divide value for the peripheral clock. At the end of reset, it is loaded with either 0000 or 0111 depending on FTFL_FOPT[LPBOOT]. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Divide-by-1. Divide-by-2. Divide-by-3. Divide-by-4. Divide-by-5.
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Memory map and register definition SIM_CLKDIV1 field descriptions (continued) Field 15–0 Reserved Description This read-only field is reserved and always has the value zero. 12.2.
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Chapter 12 System Integration Module (SIM) 12.2.14 Flash Configuration Register 1 (SIM_FCFG1) The reset value of EESIZE and DEPART are based on user programming in user IFR via the PGMPART flash command.
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Memory map and register definition SIM_FCFG1 field descriptions (continued) Field 23–20 Reserved 19–16 EESIZE Description This read-only field is reserved and always has the value zero. EEPROM size EEPROM data size . 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010-1110 1111 Reserved Reserved Reserved 2 KB 1 KB 512 Bytes 256 Bytes 128 Bytes 64 Bytes 32 Bytes Reserved 0 Bytes 15–12 Reserved This read-only field is reserved and always has the value zero.
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Chapter 12 System Integration Module (SIM) 12.2.
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Memory map and register definition SIM_FCFG2 field descriptions (continued) Field Description 15–0 Reserved This read-only field is reserved and always has the value zero. 12.2.
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Chapter 12 System Integration Module (SIM) 12.2.18 Unique Identification Register Mid Low (SIM_UIDML) Address: SIM_UIDML is 4004_7000h base + 105Ch offset = 4004_805Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UID R W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: • Reset value loaded during System Reset from Flash IFR.x = Undefined at reset.
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Functional description K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 252 Freescale Semiconductor, Inc.
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Chapter 13 Reset Control Module (RCM) 13.1 Introduction This chapter describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. 13.2 Reset memory map and register descriptions The reset control module (RCM) registers provide reset status information and reset filter control.
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Reset memory map and register descriptions • • • • LVD (without POR) — 0x02 VLLS mode wakeup due to RESET pin assertion — 0x41 VLLS mode wakeup due to other wakeup sources — 0x01 Other reset — a bit is set if its corresponding reset source caused the reset Address: RCM_SRS0 is 4007_F000h base + 0h offset = 4007_F000h Bit Read Write Reset 7 6 5 4 3 2 1 0 POR PIN WDOG 0 LOL LOC LVD WAKEUP 1 0 0 0 0 0 1 0 RCM_SRS0 field descriptions Field 7 POR Description Power-on reset Indicates
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Chapter 13 Reset Control Module (RCM) RCM_SRS0 field descriptions (continued) Field Description 0 1 1 LVD Low-voltage detect reset If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is also set by POR. 0 1 0 WAKEUP Reset not caused by a loss of external clock. Reset caused by a loss of external clock.
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Reset memory map and register descriptions RCM_SRS1 field descriptions (continued) Field Description 6 Reserved This read-only field is reserved and always has the value zero. 5 SACKERR Stop Mode Acknowledge Error Reset Indicates a reset was caused, after an attempt to enter stop mode, by a failure of one or more peripherals to acknowledge within approximately one second to enter stop mode.
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Chapter 13 Reset Control Module (RCM) 13.2.3 Reset Pin Filter Control Register (RCM_RPFC) NOTE The reset values of bits 2-0 are for Chip POR only. They are unaffected by other reset types. NOTE The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled or when entering any low leakage stop mode .
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Reset memory map and register descriptions 13.2.4 Reset Pin Filter Width Register (RCM_RPFW) NOTE The reset values of the bits in the RSTFLTSEL field are for Chip POR only. They are unaffected by other reset types. Address: RCM_RPFW is 4007_F000h base + 5h offset = 4007_F005h Bit Read Write Reset 7 6 5 4 3 0 0 0 2 1 0 0 0 RSTFLTSEL 0 0 0 0 RCM_RPFW field descriptions Field 7–5 Reserved 4–0 RSTFLTSEL Description This read-only field is reserved and always has the value zero.
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Chapter 13 Reset Control Module (RCM) RCM_RPFW field descriptions (continued) Field Description 11000 11001 11010 11011 11100 11101 11110 11111 Bus clock filter count is 25 Bus clock filter count is 26 Bus clock filter count is 27 Bus clock filter count is 28 Bus clock filter count is 29 Bus clock filter count is 30 Bus clock filter count is 31 Bus clock filter count is 32 13.2.
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Reset memory map and register descriptions K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 260 Freescale Semiconductor, Inc.
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Chapter 14 System Mode Controller 14.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The system mode controller (SMC) is responsible for sequencing the system into and out of all low power stop and run modes. Specifically, it monitors events to trigger transitions between power modes while controlling the power, clocks, and memories of the system to achieve the power consumption and functionality of that mode.
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Modes of operation ARM CPU mode MCU mode Sleep Wait Deep Sleep Stop Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the Freescale MCU documentation normally uses wait and stop. In addition, Freescale MCUs also augment stop, wait, and run modes in a number of ways. The power management controller (PMC) contains a run and a stop mode regulator. Run regulation is used in normal run, wait and stop modes.
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Chapter 14 System Mode Controller Table 14-1. Power modes (continued) Mode Description LLS The core clock and system clock to the ARM Cortex-M4 core is shut off. System clock and bus clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by reducing the voltage to internal logic. Internal logic states are retained. VLLS3 The core clock and system clock to the ARM Cortex-M4 core is shut off.
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Memory map and register descriptions 14.3.1 Power Mode Protection Register (SMC_PMPROT) This register provides protection for entry into any low power run or stop mode. The actual enabling of the low power run or stop mode occurs by configuring the power mode control register (PMCTRL). The PMPROT register can be written only once after any system reset. If the MCU is configured for a disallowed or reserved power mode, the MCU remains in its current power mode.
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Chapter 14 System Mode Controller SMC_PMPROT field descriptions (continued) Field 2 Reserved 1 AVLLS Description This read-only field is reserved and always has the value zero. Allow very low leakage stop mode Provided the appropriate control bits are set up in PMCTRL, this write once bit allows the MCU to enter any very low leakage stop mode (VLLSx). 0 1 0 Reserved Any VLLSx mode is not allowed Any VLLSx mode is allowed This read-only field is reserved and always has the value zero. 14.3.
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Memory map and register descriptions SMC_PMCTRL field descriptions (continued) Field 6–5 RUNM Description Run Mode Control When written, this field causes entry into the selected run mode. Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. This field is cleared by hardware on any exit to normal RUN mode. NOTE: RUNM should only be set to VLPR when PMSTAT=RUN. Once written to VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
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Chapter 14 System Mode Controller 14.3.3 VLLS Control Register (SMC_VLLSCTRL) The VLLSCTRL register selects which VLLSx mode is entered if STOPM=VLLS and controls power to FlexRAM during VLLS2. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details. for more information.
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Functional Description 14.3.4 Power Mode Status Register (SMC_PMSTAT) PMSTAT is a read-only, one-hot register which indicates the current power mode of the system. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details. for more information.
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Chapter 14 System Mode Controller Any reset VLPW 4 5 1 VLPR WAIT 3 RUN 6 7 2 STOP VLPS 10 8 9 VLLSx LLS 11 Figure 14-5. Power mode state diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 14-7. Power mode transition triggers Transition # From To 1 RUN WAIT Trigger conditions Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. See note.
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Functional Description Table 14-7. Power mode transition triggers (continued) Transition # From To 2 RUN STOP Trigger conditions PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 3 STOP RUN Interrupt or Reset RUN VLPR Reduce system, bus and core frequency to 2 MHz or less, Flash access limited to 1 MHz. Set PMPROT[AVLP]=1, PMCTRL[RUNM]=10.
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Chapter 14 System Mode Controller Table 14-7. Power mode transition triggers (continued) Transition # From To 8 RUN VLLSx VLLSx RUN 9 VLPR VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, VLLSCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. 10 RUN LLS PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core.
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Functional Description Reset Control Module LowLeakage Wakeup CPU (RCM) (LLWU) Stop/Wait LP exit LP exit System Mode Controller CCM low power bus (SMC) Clock Control Module Bus masters low power bus (non-CPU) Bus slaves low power bus (CCM) PMC low power bus MCG enable System Power (PMC) System Clocks (MCG) Flash low power bus Flash Memory Module Figure 14-6. Low-power system components and connections 14.4.2.
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Chapter 14 System Mode Controller 14.4.2.2 Stop mode exit sequence Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The following sequence then executes to restore the system to a run mode (RUN or VLPR): 1. The on-chip regulator in the PMC and internal power switches are restored. 2. Clock generators are enabled in the MCG. 3. System and bus clocks are enabled to all masters and slaves. 4.
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Functional Description 14.4.3 Run modes The device contains two different run modes: • Run • Very Low-Power Run (VLPR) 14.4.3.1 RUN mode This is the normal operating mode for the device. This mode is selected after any reset. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR): • The processor reads the start SP (SP_main) from vector-table offset 0x000 • The processor reads the start PC from vector-table offset 0x004 • LR is set to 0xFFFF_FFFF.
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Chapter 14 System Mode Controller fast load transitions. In addition, do not modify the clock source in the MCG module, the module clock enables in the SIM, or any clock divider registers. To reenter Normal Run mode, clear RUNM. The PMSTAT register is a read-only status register that can be used to determine when the system has completed an exit to RUN mode. When PMSTAT=RUN, the system is in run regulation and the MCU can run at full speed in any clock mode.
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Functional Description In VLPW, the on-chip voltage regulator remains in its stop regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency. To further reduce power in this mode, disable the clocks to unused modules by clearing the peripherals' corresponding clock gating control bits in the SIM. VLPR mode restrictions also apply to VLPW. VLPW mode provides the option to return to fully-regulated normal RUN mode if any enabled interrupt occurs.
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Chapter 14 System Mode Controller 14.4.5.1 STOP mode STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core. The MCG module can be configured to leave the reference clocks running. A module capable of providing an asynchronous interrupt to the device takes the device out of STOP mode and returns the device to normal RUN mode. Refer to the device's Power Management chapter for peripheral, I/O, and memory operation in STOP mode.
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Functional Description 14.4.5.3 Low-Leakage Stop (LLS) mode Low-Leakage Stop (LLS) mode can be entered from normal RUN or VLPR modes. The MCU enters LLS mode if: • In Sleep-Now or Sleep-On-Exit mode, SLEEPDEEP is set in the System Control Register in the ARM core, and • The device is configured as shown in Table 14-7. In LLS, the on-chip voltage regulator is in stop regulation. Most of the peripherals are put in a state-retention mode that does not allow them to operate while in LLS.
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Chapter 14 System Mode Controller In VLLS, the on-chip voltage regulator is in its stop-regulation state while most digital logic is powered off. In VLLS, configure the LLWU module to enable the desired wakeup sources. The available wakeup sources in VLLS are detailed LLWU's chip configuration details for this device. When entering VLLS, each I/O pin is latched as configured before executing VLLS. Because all digital logic in the MCU is powered off, all port and peripheral data is lost during VLLS.
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Functional Description the Reset Controller logic to hold the system in reset after the next recovery from a VLLS mode. This bit allows the debugger time to reinitialize the debug module before the debug session continues. The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge (VLLDBGACK) bit that is set to release the ARM core being held in reset following a VLLS recovery.
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Chapter 15 Power Management Controller 15.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The power management controller (PMC) contains the internal voltage regulator, power on reset (POR), and low voltage detect system. 15.
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Low-voltage detect (LVD) system • The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF bit is set when the supply voltage falls below the selected trip point (VLVD). The LVDF bit is cleared by writing one to the LVDACK bit, but only if the internal supply has returned above the trip point; otherwise, the LVDF bit remains set. • The low voltage warning flag (LVWF) operates in a level sensitive manner.
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Chapter 15 Power Management Controller 15.4 I/O retention When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full regulation, and releases the logic from state retention mode. The I/O are released immediately after a wakeup or reset event. In the case of LLS exit via a RESET pin, the I/O default to their reset state.
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Memory map and register descriptions While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect systems that must have LVD always on, configure the SMC's power mode protection register (PMPROT) to disallow any very low power or low leakage modes from being enabled. See the device's data sheet for the exact LVD trip voltages. NOTE The LVDV bits are reset solely on a POR Only event.
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Chapter 15 Power Management Controller PMC_LVDSC1 field descriptions (continued) Field Description 00 01 10 11 Low trip point selected (V LVD = V LVDL ) High trip point selected (V LVD = V LVDH ) Reserved Reserved 15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2) This register contains status and control bits to support the low voltage warning function. While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC2 settings.
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Memory map and register descriptions PMC_LVDSC2 field descriptions (continued) Field 5 LVWIE Description Low-Voltage Warning Interrupt Enable Enables hardware interrupt requests for LVWF. 0 1 4–2 Reserved 1–0 LVWV Hardware interrupt disabled (use polling) Request a hardware interrupt when LVWF = 1 This read-only field is reserved and always has the value zero. Low-Voltage Warning Voltage Select Selects the LVW trip point voltage (VLVW). The actual voltage for the warning depends on LVDSC1[LVDV].
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Chapter 15 Power Management Controller PMC_REGSC field descriptions (continued) Field Description BGEN controls whether the bandgap is enabled in lower power modes of operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage reference in low power modes of operation, set BGEN to continue to enable the bandgap operation. NOTE: When the bandgap voltage reference is not needed in low power modes, clear BGEN to avoid excess power consumption.
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Memory map and register descriptions K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 288 Freescale Semiconductor, Inc.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The LLWU module allows the user to select up to 16 external pin sources and up to 8 internal modules as a wakeup source from low-leakage power modes. The input sources are described in the device's chip configuration details. Each of the available wakeup sources can be individually enabled.
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Introduction • External pin wakeup inputs, each of which is programmable as falling-edge, risingedge, or any change • Wakeup inputs that are activated if enabled after MCU enters a low-leakage power mode • Optional digital filters provided to qualify an external pin detect and RESET pin detect. When entering VLLS0, the filters are disabled and bypassed. 16.1.2 Modes of operation The LLWU module becomes functional on entry into a low-leakage power mode.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) When theRESET pin filter or wakeup pin filters are enabled, filter operation begins immediately. If a low leakage mode is entered within 5 LPO clock cycles of an active edge, the edge event will be detected by the LLWU. For RESET pin filtering, this means that there is no restart to the minimum LPO cycle duration as the filtering transitions from a non-low leakage filter, which is implemented in the RCM, to the LLWU filter. 16.1.2.
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LLWU signal descriptions enter low leakge mode WUME7 Interrupt module flag detect Module7 interrupt flag (LLWU_M7IF) LLWU_MWUF7 occurred Internal module sources Interrupt module flag detect Module0 interrupt flag (LLWU_M0IF) FILT1[FILTSEL] LLWU_MWUF0 occurred WUME0 LPO LLWU_P15 Synchronizer LLWU_P0 Edge detect Pin filter 1 LPO Synchronizer FILT1[FILTE] Pin filter 1 wakeup occurred LLWU controller FILT2[FILTE] Edge detect Pin filter 2 exit low leakge mode Pin filter 2 wakeup occurred in
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.
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Memory map/register definition 16.3.1 LLWU Pin Enable 1 register (LLWU_PE1) LLWU_PE1 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P3-LLWU_P0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_PE1 field descriptions (continued) Field Description 01 10 11 External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 16.3.2 LLWU Pin Enable 2 register (LLWU_PE2) LLWU_PE2 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P7-LLWU_P4.
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Memory map/register definition LLWU_PE2 field descriptions (continued) Field Description 01 10 11 1–0 WUPE4 External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P4 Enables and configures the edge detection for the wakeup pin.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_PE3 field descriptions (continued) Field Description 01 10 11 3–2 WUPE9 Wakeup Pin Enable For LLWU_P9 Enables and configures the edge detection for the wakeup pin.
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Memory map/register definition LLWU_PE4 field descriptions (continued) Field Description 10 11 5–4 WUPE14 Wakeup Pin Enable For LLWU_P14 Enables and configures the edge detection for the wakeup pin.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_ME field descriptions Field 7 WUME7 Description Wakeup Module Enable For Module 7 Enables an internal module as a wakeup source input. 0 1 6 WUME6 Wakeup Module Enable For Module 6 Enables an internal module as a wakeup source input. 0 1 5 WUME5 Enables an internal module as a wakeup source input. Enables an internal module as a wakeup source input. Enables an internal module as a wakeup source input.
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Memory map/register definition 16.3.6 LLWU Flag 1 register (LLWU_F1) LLWU_F1 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if the associated WUPEx bit is cleared.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_F1 field descriptions (continued) Field 4 WUF4 Description Wakeup Flag For LLWU_P4 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF4. 0 1 3 WUF3 Wakeup Flag For LLWU_P3 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF3.
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Memory map/register definition NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_F2 field descriptions (continued) Field 2 WUF10 Description Wakeup Flag For LLWU_P10 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF10. 0 1 1 WUF9 Wakeup Flag For LLWU_P9 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF9.
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Memory map/register definition LLWU_F3 field descriptions Field 7 MWUF7 Description Wakeup flag For module 7 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 6 MWUF6 Wakeup flag For module 6 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_F3 field descriptions (continued) Field Description Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 Module 0 input was not a wakeup source Module 0 input was a wakeup source 16.3.
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Memory map/register definition LLWU_FILT1 field descriptions (continued) Field 3–0 FILTSEL Description Filter Pin Select Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 ... 1111 Select LLWU_P0 for filter ... Select LLWU_P15 for filter 16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2) LLWU_FILT2 is a control and status register that is used to enable/disable the digital filter 2 features for an external pin.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_FILT2 field descriptions (continued) Field 3–0 FILTSEL Description Filter Pin Select Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 ... 1111 Select LLWU_P0 for filter ... Select LLWU_P15 for filter 16.3.11 LLWU Reset Enable register (LLWU_RST) LLWU_RST is a control register that is used to enable/disable the digital filter for the external pin detect and RESET pin.
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Functional description 16.4 Functional description This on-chip peripheral module is called a low-leakage wakeup unit (LLWU) module because it allows internal peripherals and external input pins as a source of wakeup from low-leakage modes. It is operational only in LLS and VLLSx modes. The LLWU module contains pin enables for each external pin and internal module. For each external pin, the user can disable or select the edge type for the wakeup.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.4.2 VLLS modes In the case of a wakeup due to external pin or internal module wakeup, recovery is always via a reset flow and the RCM_SRS[WAKEUP] is set indicating the low-leakage mode was active. State retention data is lost and I/O will be restored after PMC_REGSC[ACKISO] has been written. A VLLS exit event due to RESET pin assertion causes an exit via a system reset. State retention data is lost and the I/O states immediately return to their reset state.
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Functional description K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 310 Freescale Semiconductor, Inc.
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Chapter 17 Miscellaneous Control Module (MCM) 17.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 17.1.1 Features The MCM includes the following features: • Program-visible information on the platform configuration and revision 17.
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Memory Map/Register Descriptions MCM memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page E008_000A Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) 16 R 000Fh 17.2.2/312 E008_000C Crossbar Switch (AXBS) Control Register (MCM_PLACR) 32 R/W 0000_0000h 17.2.3/313 17.2.
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Chapter 17 Miscellaneous Control Module (MCM) MCM_PLAMC field descriptions Field Description 15–8 Reserved This read-only field is reserved and always has the value zero. 7–0 AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 1 A bus master connection to AXBS input port n is absent A bus master connection to AXBS input port n is present 17.2.
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Memory Map/Register Descriptions K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 314 Freescale Semiconductor, Inc.
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Chapter 18 Crossbar Switch Lite (AXBS-Lite) 18.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This chapter provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure.
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Memory Map / Register Definition 18.2 Memory Map / Register Definition This design was meant to be as small as possible. To help achieve this, the crossbar switch contains no memory-mapped registers for configuring. 18.3 Functional Description 18.3.1 General operation When a master accesses the crossbar switch the access is immediately taken. If the targeted slave port of the access is available, then the access is immediately presented on the slave port.
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Chapter 18 Crossbar Switch Lite (AXBS-Lite) The crossbar terminates all master IDLE transfers, as opposed to allowing the termination to come from one of the slave buses. Additionally, when no master is requesting access to a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default master may be granted access to the slave port. When a slave bus is being idled by the crossbar, it remains parked with the last master to use the slave port .
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Initialization/application information Table 18-1. How AXBS grants control of a slave port to a master (continued) When Then AXBS grants control to the requesting master Both of the following are true: At the next arbitration point for the undefined length burst • The current master is running an undefined length transfer burst transfer. • The requesting master's priority level is higher than that NOTE: Arbitration points for an undefined length burst are defined in the MGPCR for each master.
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Chapter 19 Peripheral Bridge (AIPS-Lite) 19.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The peripheral bridge (AIPS-Lite) converts the crossbar switch interface to an interface to access a majority of peripherals on the device. The peripheral bridge supports up to 128 peripherals. The bridge includes separate clock enable inputs for each of the slots to accommodate slower peripherals. 19.1.
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Functional description • • • • • Module enables The module address Transfer attributes Byte enables Write data The peripheral bridge captures read data from the peripheral interface and drives it to the crossbar switch. Each peripheral is allocated one block of the memory map. Two global external module enables are available for the remaining address space to allow for customization and expansion of addressed peripheral devices. 19.
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Chapter 20 Direct Memory Access Multiplexer (DMAMUX) 20.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 20.1.1 Overview The direct memory access multiplexer (DMAMUX) routes DMA sources, called slots, to any of the DMA channels. This process is illustrated in the following figure. K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 Freescale Semiconductor, Inc.
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Introduction DMAMUX Source #1 DMA Channel #0 DMA Channel #1 Source #2 Source #3 Source #x Always #1 Always #y Trigger #1 DMA Channel #n Trigger #z Figure 20-1. DMAMUX block diagram 20.1.2 Features The DMA channel MUX provides these features: • 52 peripheral slots and 10 always-on slots can be routed to channels. • independently selectable DMA channel routers. • The first 4 channels additionally provide a trigger functionality.
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Chapter 20 Direct Memory Access Multiplexer (DMAMUX) In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place, for example, changing the period of a DMA trigger.
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Memory map/register definition DMAMUX memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4002_1004 Channel Configuration register (DMAMUX0_CHCFG4) 8 R/W 00h 20.3.1/324 4002_1005 Channel Configuration register (DMAMUX0_CHCFG5) 8 R/W 00h 20.3.1/324 4002_1006 Channel Configuration register (DMAMUX0_CHCFG6) 8 R/W 00h 20.3.1/324 4002_1007 Channel Configuration register (DMAMUX0_CHCFG7) 8 R/W 00h 20.3.
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Chapter 20 Direct Memory Access Multiplexer (DMAMUX) DMAMUXx_CHCFGn field descriptions (continued) Field Description 0 1 6 TRIG DMA Channel Trigger Enable Enables the periodic trigger capability for the triggered DMA channel. 0 1 5–0 SOURCE DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. DMA channel is enabled Triggering is disabled.
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Functional description Note Because of the dynamic nature of the system (i.e. DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed. Source #1 Source #2 Source #3 Trigger #1 Trigger #2 DMA Channel #0 DMA Channel #1 Source #x Always #1 Trigger #4 DMA Channel #3 Always #y Figure 20-36.
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Chapter 20 Direct Memory Access Multiplexer (DMAMUX) After the DMA request has been serviced, the peripheral will negate its request, effectively resetting the gating mechanism until the peripheral re-asserts its request AND the next trigger event is seen. This means that if a trigger is seen, but the peripheral is not requesting a transfer, then that trigger will be ignored. This situation is illustrated in the following figure. Peripheral Request Trigger DMA Request Figure 20-38.
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Functional description 20.4.3 "Always enabled" DMA sources In addition to the peripherals that can be used as DMA sources, there are 10 additional DMA sources that are "always enabled". Unlike the peripheral DMA sources, where the peripheral controls the flow of data during DMA transfers, the "always enabled" sources provide no such "throttling" of the data transfers.
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Chapter 20 Direct Memory Access Multiplexer (DMAMUX) be continuous (DMA triggering is disabled) or can use the DMA triggering capability. In this manner, it is possible to execute periodic transfers of packets of data from one source to another, without processor intervention. 20.5 Initialization/application information This section provides instructions for initializing the DMA channel MUX. 20.5.1 Reset The reset state of each individual bit is shown in Memory map/register definition.
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Initialization/application information volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile volatile unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned char char char char char char char char char char char char *CHCONFIG4 = *CHCONFIG5 = *CHCONFIG6 = *CHCONFIG7 = *CHCONFIG8 = *CHCONFIG9 = *CHCONFIG10= *CHCONFIG11= *CHCONFIG12= *CHCONFIG13= *CHCONFIG14= *CHCONFIG15= (volatile (volatile (volatile (volati
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Chapter 20 Direct Memory Access Multiplexer (DMAMUX) #include "registers.h" : : *CHCONFIG2 = 0x00; *CHCONFIG2 = 0x85; Disabling a source A particular DMA source may be disabled by not writing the corresponding source value into any of the CHCFG registers. Additionally, some module-specific configuration may be necessary. See the appropriate section for more details. To switch the source of a DMA channel: 1. Disable the DMA channel in the DMA and re-configure the channel for the new source. 2.
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Initialization/application information K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 332 Freescale Semiconductor, Inc.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor.
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Introduction eDMA Write Address Write Data 0 Transfer Control Descriptor (TCD) n-1 64 eDMA Engine Program Model/ Channel Arbitration Read Data Read Data Internal Peripheral Bus To/From Crossbar Switch 1 2 Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 21-1. eDMA block diagram 21.1.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory.
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Chapter 21 Direct Memory Access Controller (eDMA) Table 21-1. eDMA engine submodules Submodule Address path Function This block implements registered versions of two channel transfer control descriptors, channel x and channel y, and manages all master bus-address calculations. All the channels provide the same functionality.
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Introduction Table 21-2. Transfer control descriptor memory Submodule Description Memory controller This logic implements the required dual-ported controller, managing accesses from the eDMA engine as well as references from the internal peripheral bus. As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled. Memory array TCD storage is implemented using a single-port, synchronous RAM array. 21.1.
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Chapter 21 Direct Memory Access Controller (eDMA) • One interrupt per channel, optionally asserted at completion of major iteration count • Optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller • Optional support for scatter/gather DMA processing • Support for complex data structures • Support to cancel transfers via software In the discussion of this module, n is used to reference the channel number. 21.
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Memory map/register definition • The first region defines a number of registers providing control functions • The second region corresponds to the local transfer control descriptor memory Each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1,... channel 3 . Each TCDn definition is presented as 11 registers of 16 or 32 bits.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) 4000_801E Register name Width Access (in bits) Clear Error Register (DMA_CERR) Reset value Section/ page 8 W (always reads zero) 00h 21.3.11/ 354 00h 21.3.12/ 355 4000_801F Clear Interrupt Request Register (DMA_CINT) 8 W (always reads zero) 4000_8024 Interrupt Request Register (DMA_INT) 32 R/W 0000_0000h 21.3.13/ 355 4000_802C Error Register (DMA_ERR) 32 R/W 0000_0000h 21.3.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9016 DMA_TCD0_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 368 4000_9018 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD0_DLASTSGA) 32 R/W Undefined 21.3.28/ 369 4000_901C TCD Control and Status (DMA_TCD0_CSR) 16 R/W Undefined 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_903E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD1_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 373 4000_9040 TCD Source Address (DMA_TCD2_SADDR) 32 R/W Undefined 21.3.17/ 360 4000_9044 TCD Signed Source Address Offset (DMA_TCD2_SOFF) 16 R/W Undefined 21.3.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9068 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD3_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 362 4000_9068 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD3_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) NOTE For proper operation, writes to the CR register must be performed only when the DMA channels are inactive; that is, when TCDn_CSR[ACTIVE] bits are cleared.
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Memory map/register definition DMA_CR field descriptions (continued) Field Description 0 1 4 HOE Normal operation Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. Halt On Error 0 1 3 Reserved Normal operation Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. This read-only field is reserved and always has the value zero.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_ES field descriptions Field 31 VLD 30–17 Reserved 16 ECX 15 Reserved 14 CPE Description Logical OR of all ERR status bits 0 1 No ERR bits are set At least one ERR bit is set indicating a valid error exists that has not been cleared This read-only field is reserved and always has the value zero.
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Memory map/register definition DMA_ES field descriptions (continued) Field Description • TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or • TCDn_CITER[CITER] is equal to zero, or • TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] 2 SGE Scatter/Gather Configuration Error 1 SBE Source Bus Error 0 DBE Destination Bus Error 0 1 0 1 0 1 No scatter/gather configuration error The last recorded error was a configuration error detected in the TCDn_DLASTSGA field.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_ERQ field descriptions (continued) Field Description 3 ERQ3 Enable DMA Request 3 2 ERQ2 Enable DMA Request 2 1 ERQ1 Enable DMA Request 1 0 ERQ0 Enable DMA Request 0 0 1 0 1 0 1 0 1 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Th
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Memory map/register definition DMA_EEI field descriptions (continued) Field Description 0 1 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request 2 EEI2 Enable Error Interrupt 2 1 EEI1 Enable Error Interrupt 1 0 EEI0 Enable Error Interrupt 0 0 1 0 1 0 1 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corr
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_CEEI field descriptions (continued) Field 1–0 CEEI Description Clear Enable Error Interrupt Clears the corresponding bit in EEI 21.3.6 Set Enable Error Interrupt Register (DMA_SEEI) The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be set.
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Memory map/register definition 21.3.7 Clear Enable Request Register (DMA_CERQ) The CERQ provides a simple memory-mapped mechanism to clear a given bit in the ERQ to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a global clear function, forcing the entire contents of the ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the command is ignored.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.8 Set Enable Request Register (DMA_SERQ) The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ to enable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be set. Setting the SAER bit provides a global set function, forcing the entire contents of ERQ to be set. If the NOP bit is set, the command is ignored.
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Memory map/register definition 21.3.9 Clear DONE Status Bit Register (DMA_CDNE) The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared. Setting the CADN bit provides a global clear function, forcing all DONE bits to be cleared. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.10 Set START Bit Register (DMA_SSRT) The SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set. Setting the SAST bit provides a global set function, forcing all START bits to be set. If the NOP bit is set, the command is ignored.
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Memory map/register definition 21.3.11 Clear Error Register (DMA_CERR) The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a global clear function, forcing the ERR contents to be cleared, clearing all channel error indicators. If the NOP bit is set, the command is ignored.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.12 Clear Interrupt Request Register (DMA_CINT) The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the INT to be cleared. Setting the CAIR bit provides a global clear function, forcing the entire contents of the INT to be cleared, disabling all DMA interrupt requests.
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Memory map/register definition The state of any given channel’s interrupt request is directly affected by writes to this register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit position clears the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding channel’s current interrupt status.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.14 Error Register (DMA_ERR) The ERR provides a bit map for the 4 channels, signaling the presence of an error for each channel. The eDMA engine signals the occurrence of an error condition by setting the appropriate bit in this register. The outputs of this register are enabled by the contents of the EEI, and then routed to the interrupt controller.
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Memory map/register definition DMA_ERR field descriptions (continued) Field Description 1 ERR1 Error In Channel 1 0 ERR0 Error In Channel 0 0 1 0 1 An error in the corresponding channel has not occurred An error in the corresponding channel has occurred An error in the corresponding channel has not occurred An error in the corresponding channel has occurred 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_HRS field descriptions (continued) Field Description 1 HRS1 Hardware Request Status Channel 1 0 HRS0 Hardware Request Status Channel 0 0 1 0 1 A hardware service request for the corresponding channel is not present A hardware service request for the corresponding channel is present A hardware service request for the corresponding channel is not present A hardware service request for the corresponding channel is present 21.3.
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Memory map/register definition DMA_DCHPRIn field descriptions (continued) Field Description 5–2 Reserved This read-only field is reserved and always has the value zero. 1–0 CHPRI Channel n Arbitration Priority Channel priority when fixed-priority arbitration is enabled NOTE: Reset value for the channel priority fields, CHPRI, is equal to the corresponding channel number for each priority register, i.e., DCHPRI3[CHPRI] equals 0b11. 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_SOFF field descriptions Field Description 15–0 SOFF Source address signed offset Sign-extended offset applied to the current source address to form the next-state value as each source read is completed. 21.3.
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Memory map/register definition DMA_TCDn_ATTR field descriptions (continued) Field Description 7–3 DMOD Destination Address Modulo 2–0 DSIZE Destination Data Transfer Size See the SMOD definition See the SSIZE definition 21.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD_NBYTES_MLNO) TCD word 2's register definition depends on the status of minor loop mapping. If minor loop mapping is disabled (CR[EMLM] = 0), TCD word 2 is defined as follows.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD_NBYTES_MLOFFNO) TCD word 2 is defined as follows if: • Minor loop mapping is enabled (CR[EMLM] = 1) and • SMLOE = 0 and DMLOE = 0 If minor loop mapping is enabled and SMLOE or DMLOE is set then refer to the TCD_NBYTES_MLOFFYES register description.
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Memory map/register definition 21.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD_NBYTES_MLOFFYES) TCD word 2 is defined as follows if: • Minor loop mapping is enabled (CR[EMLM] = 1) and • Minor loop offset enabled (SMLOE or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared then refer to the TCD_NBYTES_MLOFFNO register description.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_NBYTES_MLOFFYES field descriptions (continued) Field Description preemption.) After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. 21.3.
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Memory map/register definition DMA_TCDn_DADDR field descriptions Field Description 31–0 DADDR Destination Address Memory address pointing to the destination data. 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD_CITER_ELINKYES) If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
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Memory map/register definition DMA_TCDn_CITER_ELINKYES field descriptions (continued) Field Description final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the CITER field from the beginning iteration count (BITER) field. NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_CITER_ELINKNO field descriptions (continued) Field Description 14–0 CITER Current Major Iteration Count This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel. It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations (e.g.
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Memory map/register definition 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_CSR field descriptions (continued) Field Description This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count reaches zero; The software clears it, or the hardware when the channel is activated. NOTE: This bit must be cleared to write the MAJORELINK or ESG bits. 6 ACTIVE 5 MAJORELINK Channel Active This flag signals the channel is currently in execution.
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Memory map/register definition DMA_TCDn_CSR field descriptions (continued) Field Description If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero. 0 1 0 START The end-of-major loop interrupt is disabled The end-of-major loop interrupt is enabled Channel Start If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after the channel begins execution.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_BITER_ELINKYES field descriptions (continued) Field Description 0 1 14–11 Reserved The channel-to-channel linking is disabled The channel-to-channel linking is enabled This read-only field is reserved and always has the value zero.
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Functional description DMA_TCDn_BITER_ELINKNO field descriptions Field Description 15 ELINK Enables channel-to-channel linking on minor loop complete As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel.
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Chapter 21 Direct Memory Access Controller (eDMA) eDMA Write Address Write Data 0 Transfer Control Descriptor (TCD) 64 eDMA Engine Program Model/ Channel Arbitration Read Data n-1 Internal Peripheral Bus To/From Crossbar Switch 1 2 Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 21-98. eDMA operation, part 1 This example uses the assertion of the eDMA peripheral request signal to request service for channel n.
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Functional description eDMA Write Address Write Data To/From Crossbar Switch Transfer Control Descriptor (TCD) n-1 64 eDMA Engine Program Model/ Channel Arbitration Read Data Internal Peripheral Bus 0 1 2 Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 21-99.
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Chapter 21 Direct Memory Access Controller (eDMA) eDMA Write Address Write Data To/From Crossbar Switch Transfer Control Descriptor (TCD) n-1 64 Internal Peripheral Bus 0 1 2 eDMA En g in e Program Model/ Channel Arbitration Read Data Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 21-100. eDMA operation, part 3 21.4.
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Functional description • All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. • In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal. All channel priority levels must be unique when fixed arbitration mode is enabled.
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Chapter 21 Direct Memory Access Controller (eDMA) loop complete indicators, setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is detected. After the error status has been updated, the eDMA engine continues operating by servicing the next appropriate channel. A channel that experiences an error condition is not automatically disabled.
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Functional description address spaces remains important. However, the microarchitecture of the eDMA also factors significantly into the resulting metric. 21.4.4.1 Peak transfer rates The peak transfer rates for several different source and destination transfers are shown in the following tables.
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Chapter 21 Direct Memory Access Controller (eDMA) The eDMA design supports the following hardware service request sequence. Note that the exact timing from Cycle 7 is a function of the response times for the channel's read and write accesses. In the case of an internal peripheral bus read and internal SRAM write, the combined data phase time is 4 cycles. For an SRAM read and internal peripheral bus write, it is 5 cycles. Table 21-102.
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Functional description be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle x +5. The resulting peak request rate, as a function of the system frequency, is shown in the following table. Table 21-103. eDMA peak request rate (MReq/sec) Request rate Request rate with zero wait states with wait states 66.6 7.4 5.8 83.3 9.2 7.2 100.0 11.1 8.7 133.3 14.8 11.6 150.0 16.6 13.
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Chapter 21 Direct Memory Access Controller (eDMA) PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 Mreq/sec For an internal peripheral bus to SRAM transfer, PEAKreq = 150 MHz / [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 Mreq/sec Assuming an even distribution of the two transfer types, the average peak request rate would be: PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec) / 2 = 12.
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Initialization/application information 3. Enable error interrupts in the EEI register if so desired. 4. Write the 32-byte TCD for each channel that may request service. 5. Enable any hardware service requests via the ERQ register. 6.
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Chapter 21 Direct Memory Access Controller (eDMA) Current major loop iteration count (CITER) Source or destination memory Minor loop DMA request 3 Major loop Minor loop DMA request 2 Minor loop DMA request 1 Figure 21-101. Example of multiple loop iterations The following figure lists the memory array terms and how the TCD settings interrelate.
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Initialization/application information For all error types other than channel priority error, the channel number causing the error is recorded in the ES register. If the error source is not removed before the next activation of the problem channel, the error is detected and recorded again. If priority levels are not unique, when any channel requests service, a channel priority error is reported.
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Chapter 21 Direct Memory Access Controller (eDMA) programmed in increments to match the transfer size: one byte for the source and four bytes for the destination. The final source and destination addresses are adjusted to return to their beginning values.
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Initialization/application information 6. The eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 1 (TCDn_BITER). 7. The eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 1. 8. The channel retires and the eDMA goes idle or services the next channel. 21.5.4.2 Multiple requests The following example transfers 32 bytes via two hardware requests, but is otherwise the same as the previous example.
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Chapter 21 Direct Memory Access Controller (eDMA) g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. h. Write 32-bits to location 0x200C → last iteration of the minor loop. 6. eDMA engine writes: TCDn_SADDR = 0x1010, TCDn_DADDR = 0x2010, TCDn_CITER = 1. 7. eDMA engine writes: TCDn_CSR[ACTIVE] = 0. 8. The channel retires → one iteration of the major loop. The eDMA goes idle or services the next channel. 9.
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Initialization/application information 16. The channel retires → major loop complete. The eDMA goes idle or services the next channel. 21.5.4.3 Using the modulo feature The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size of the queue is a power of 2. MOD is a 5-bit field for the source and destination in the TCD, and it specifies which lower address bits increment from their original value after the address+offset calculation.
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Chapter 21 Direct Memory Access Controller (eDMA) The TCD status bits execute the following sequence for a software activated channel: Stage TCDn_CSR bits State START ACTIVE DONE 1 1 0 0 Channel service request via software 2 0 1 0 Channel is executing 3a 0 0 0 Channel has completed the minor loop and is idle 3b 0 0 1 Channel has completed the major loop and is idle The best method to test for minor-loop completion when using hardware, that is, peripheral, initiated service reques
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Initialization/application information 21.5.5.3 Checking channel preemption status Preemption is available only when fixed arbitration is selected as the channel arbitration mode. A preemptive situation is one in which a preempt-enabled channel runs and a higher priority request becomes active. When the eDMA engine is not operating in fixed channel arbitration mode, the determination of the actively running relative priority outstanding requests become undefined.
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Chapter 21 Direct Memory Access Controller (eDMA) When minor loop linking is enabled (TCDn_CITER[E_LINK] = 1), the TCDn_CITER[CITER] field uses a nine bit vector to form the current iteration count. When minor loop linking is disabled (TCDn_CITER[E_LINK] = 0), the TCDn_CITER[CITER] field uses a 15-bit vector to form the current iteration count. The bits associated with the TCDn_CITER[LINKCH] field are concatenated onto the CITER value to increase the range of the CITER.
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Initialization/application information 21.5.7.2 Dynamic channel linking Dynamic channel linking is the process of setting the TCD.major.e_link bit during channel execution. This bit is read from the TCD local memory at the end of channel execution, thus allowing the user to enable the feature during channel execution. Because the user is allowed to change the configuration during execution, a coherency model is needed.
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Chapter 21 Direct Memory Access Controller (eDMA) is retiring the channel. The TCD.e_sg would be set in the programmer’s model, but it would be unclear whether the actual scatter/gather request was honored before the channel retired. Two methods for this coherency model are shown in the following subsections. Method 1 has the advantage of reading the major.linkch field and the e_sg bit with a single read.
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Initialization/application information If e_sg = 0b and the major.linkch (ID) did not change, the attempted dynamic link did not succeed (the channel was already retiring). If e_sg = 0b and the major.linkch (ID) changed, the dynamic link attempt was successful (the new TCD’s e_sg value cleared the e_sg bit). 21.5.7.3.2 Method 2 (channel using major loop channel linking) For a channel using major loop channel linking, the coherency model described here may be used for a dynamic scatter/gather request.
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Chapter 22 External Watchdog Monitor (EWM) 22.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The watchdog is generally used to monitor the flow and execution of embedded software within an MCU. The watchdog consists of a counter that if allowed to overflow, forces an internal reset (asynchronous) to all on-chip peripherals and optionally assert the RESET pin to reset external devices/circuits.
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Introduction • Windowed refresh option • Provides robust check that program flow is faster than expected. • Programmable window. • Refresh outside window leads to assertion of EWM_out. • Robust refresh mechanism • Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 (EWM_service_time) peripheral bus clock cycles. • One output port, EWM_out, when asserted is used to reset or place the external circuit into safe mode.
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Chapter 22 External Watchdog Monitor (EWM) 22.1.2.2 Wait Mode The EWM module treats the stop and wait modes as the same. EWM functionality remains the same in both of these modes. 22.1.2.3 Debug Mode Entry to debug mode has no effect on the EWM. • If the EWM is enabled prior to entry of debug mode, it remains enabled. • If the EWM is disabled prior to entry of debug mode, it remains disabled. 22.1.3 Block Diagram This figure shows the EWM block diagram.
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EWM Signal Descriptions 22.2 EWM Signal Descriptions The EWM has two external signals, as shown in the following table. Table 22-1. EWM Signal Descriptions Signal EWM_in EWM_out Description I/O EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. I EWM reset out signal O 22.3 Memory Map/Register Definition This section contains the module memory map and registers.
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Chapter 22 External Watchdog Monitor (EWM) Address: EWM_CTRL is 4006_1000h base + 0h offset = 4006_1000h Bit Read Write Reset 7 6 5 4 0 0 0 0 3 2 1 0 INTEN INEN ASSIN EWMEN 0 0 0 0 0 EWM_CTRL field descriptions Field 7–4 Reserved 3 INTEN 2 INEN 1 ASSIN 0 EWMEN Description This read-only field is reserved and always has the value zero. Interrupt Enable. This bit when set and EWM_out is asserted, an interrupt request is generated.
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Memory Map/Register Definition 22.3.3 Compare Low Register (EWM_CMPL) The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to service the EWM counter. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error.
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Chapter 22 External Watchdog Monitor (EWM) EWM_CMPH field descriptions Field 7–0 COMPAREH Description To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum service time is required. 22.4 Functional Description The following sections describe functional details of the EWM module. 22.4.
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Functional Description Note EWM_out pad must be in pull down state when EWM functionality is used and when EWM is under Reset. 22.4.2 The EWM_in Signal The EWM_in is a digital input signal that allows an external circuit to control the EWM_out signal. For example, in the application, an external circuit monitors a critical safety function, and if there is fault with this circuit's behavior, it can then actively initiate the EWM_out signal that controls the gating circuit.
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Chapter 22 External Watchdog Monitor (EWM) The EWM compare registers are used to create a service window, which is used by the CPU to service/refresh the EWM module. • If the CPU services the EWM when the counter value lies between CMPL value and CMPH value, the counter is reset to zero. This is a legal service operation. • If the CPU executes a EWM service/refresh action outside the legal service window, EWM_out is asserted. It is illegal to program CMPL and CMPH with same value.
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Functional Description K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 406 Freescale Semiconductor, Inc.
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Chapter 23 Watchdog Timer (WDOG) 23.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in case of its failure. Reasons for failure include run-away software code and the stoppage of the system clock that in a safety critical system can lead to serious consequences. In such cases, the watchdog brings the system into a safe state of operation.
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Features • You need to always update these bits after unlocking within 256 bus clock cycles. Failure to update these bits resets the system. • Programmable time-out period specified in terms of number of WDOG clock cycles. • Ability to test WDOG timer and reset with a flag indicating watchdog test. • Quick test—Small time-out value programmed for quick test. • Byte test—Individual bytes of timer tested one at a time. • Read-only access to the WDOG timer—Allows dynamic check that WDOG timer is operational.
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Chapter 23 Watchdog Timer (WDOG) 23.
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Functional overview to be serviced periodically, failing which it resets the system. This ensures that the software is executing correctly and has not run away in an unintended direction. Software can adjust the period of servicing or the time-out value for the watchdog timer to meet the needs of the application. You can select a windowed mode of operation that expects the servicing to be done only in a particular window of the time-out period.
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Chapter 23 Watchdog Timer (WDOG) The update feature is useful for applications that have an initial, non-safety critical part, where the watchdog is kept disabled or with a conveniently long time-out period. This means the application coder does not have to frequently service the watchdog. After the critical part of the application begins, the watchdog can be reconfigured as needed.
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Functional overview Updates in the write-once registers take effect only after the WCT window closes with the following exceptions for which changes take effect immediately: • Stop, Wait, and Debug mode enable • IRQ_RST_EN The operations of refreshing the watchdog goes undetected during the WCT. 23.3.3 Refreshing the watchdog A robust refreshing mechanism has been chosen for the watchdog. A valid refresh is a write of 0xA602 followed by 0xB480 within 20 bus clock cycles to watchdog refresh register.
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Chapter 23 Watchdog Timer (WDOG) time-out exception. See Generated Resets and Interrupts. You need to unlock the watchdog before enabling it. A system reset brings the watchdog out of the disabled mode. 23.3.6 Low-power modes of operation The low-power modes of operation of the watchdog are described in the following table: Table 23-1.
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Testing the watchdog 23.4 Testing the watchdog For IEC 60730 and other safety standards, the expectation is that anything that monitors a safety function must be tested, and this test is required to be fault tolerant. To test the watchdog, its main timer and its associated compare and reset logic must be tested. To this end, two tests are implemented for the watchdog, as described in Quick Test and Byte Test. A control bit is provided to put the watchdog into functional test mode.
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Chapter 23 Watchdog Timer (WDOG) 23.4.1 Quick test In this test, the time-out value of watchdog timer is programmed to a very low value to achieve quick time-out. The only difference between the quick test and the normal mode of the watchdog is that TESTWDOG is set for the quick test. This allows for a faster test of the watchdog reset mechanism. 23.4.2 Byte test The byte test is a more thorough a test of the watchdog timer.
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Backup reset generator other stages, N – 2, N – 3... and N + 1, N + 2... are enabled for the test on byte N. These disabled stages, except the most significant stage of the counter, are loaded with a value of 0xFF. 23.5 Backup reset generator The backup reset generator generates the final reset which goes out to the system.
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Chapter 23 Watchdog Timer (WDOG) The watchdog can also generate an interrupt. If IRQ_RST_EN is set, then on the above mentioned events WDOG_ST_CTRL_L[INT_FLG] is set, generating an interrupt. A watchdog reset is also generated WCT time later to ensure the watchdog is fault tolerant. The interrupt can be cleared by writing 1 to INT_FLG. The gap of WCT between interrupt and reset means that the WDOG time-out value must be greater than WCT.
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Memory map and register definition 23.7.
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Chapter 23 Watchdog Timer (WDOG) WDOG_STCTRLH field descriptions (continued) Field Description 9 Reserved This read-only field is reserved and always has the value zero. 8 Reserved This field is reserved. 7 WAITEN Enables or disables WDOG in Wait mode. 6 STOPEN Enables or disables WDOG in Stop mode. 5 DBGEN Enables or disables WDOG in Debug mode. 0 1 0 1 0 1 WDOG is disabled in CPU Wait mode. WDOG is enabled in CPU Wait mode. WDOG is disabled in CPU Stop mode.
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Memory map and register definition 23.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL) Address: WDOG_STCTRLL is 4005_2000h base + 2h offset = 4005_2002h Bit 15 Write INTFLG Read Reset 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 Reserved 0 0 0 0 0 0 0 0 WDOG_STCTRLL field descriptions Field Description 15 INTFLG Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a precondition to set this flag.
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Chapter 23 Watchdog Timer (WDOG) 23.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL) The time-out value of the watchdog must be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain.
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Memory map and register definition 23.7.6 Watchdog Window Register Low (WDOG_WINL) NOTE You must set the Window Register value lower than the Timeout Value Register.
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Chapter 23 Watchdog Timer (WDOG) 23.7.8 Watchdog Unlock register (WDOG_UNLOCK) Address: WDOG_UNLOCK is 4005_2000h base + Eh offset = 4005_200Eh Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 0 0 0 WDOGUNLOCK 1 1 0 1 1 0 0 1 0 WDOG_UNLOCK field descriptions Field Description 15–0 Writing the unlock sequence values to this register to makes the watchdog write-once registers writable WDOGUNLOCK again.
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Watchdog operation with 8-bit access WDOG_TMROUTL field descriptions Field Description 15–0 Shows the value of the lower 16 bits of the watchdog timer. TIMEROUTLOW 23.7.
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Chapter 23 Watchdog Timer (WDOG) 23.8.1 General guideline When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is to access both the bytes of a register, place the two 8-bit accesses one after the other in your code. 23.8.2 Refresh and unlock operations with 8-bit access One exception condition that generates a reset to the system is the write of any value other than those required for a legal refresh/update sequence to the respective refresh and unlock registers.
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Restrictions on watchdog operation As shown in the preceding table, the refresh register holds its reset value initially. Thereafter, two 8-bit accesses are performed on the register to write the first value of the refresh sequence. No mismatch exception is registered on the intermediate write, Write1. The sequence is completed by performing two more 8-bit accesses, writing in the second value of the sequence for a successful refresh.
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Chapter 23 Watchdog Timer (WDOG) • WCT must be equivalent to at least three watchdog clock cycles. If not ensured, this means that even after the close of the WCT window, you have to wait for the synchronized system reset to deassert in the watchdog clock domain, before expecting the configuration updates to take effect. • The time-out value of the watchdog should be set to a minimum of four watchdog clock cycles.
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Restrictions on watchdog operation watchdog clock cycle delay in the timer restarting. In case the duration of the stop mode is less than one watchdog clock cycle, the watchdog timer is not guaranteed to pause. • Consider the case when the first refresh value is written, following which the system enters stop mode with system bus clk still on. If the second refresh value is not written within 20 bus cycles of the first value, the system is reset, or interrupt-thenreset if enabled.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL). The FLL is controllable by either an internal or an external reference clock. The PLL is controllable by the external reference clock.
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Introduction • Internal or external reference clock can be used as the FLL source. • Can be used as a clock source for other on-chip peripherals. • Phase-locked loop (PLL): • Voltage-controlled oscillator (VCO) • External reference clock is used as the PLL source. • Modulo VCO frequency divider • Phase/Frequency detector • Integrated loop filter • Can be used as a clock source for other on-chip peripherals.
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Chapter 24 Multipurpose Clock Generator (MCG) • Internal Reference Clocks Auto Trim Machine (ATM) capability using an external clock as a reference • Reference dividers for both the FLL and PLL are provided • Reference dividers for the Fast Internal Reference Clock are provided • MCG PLL Clock (MCGPLLCLK) is provided as a clock source for other on-chip peripherals • MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip peripherals • MCG Fixed Frequency Clock (MCGFFCLK) is provided as a
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Introduction RTC Oscillator Crystal Oscillator External Reference Clock CLKS ATMS OSCSEL OSCINIT0 PLLCLKEN0 EREFS0 IREFS HGO0 PLLS RANGE0 MCG Crystal Oscillator Enable Detect STOP IREFSTEN Auto Trim Machine IRCLKEN SCTRIM Internal Reference SCFTRIM Clock Generator FCTRIM MCGIRCLK IRCS CLKS Slow Clock Fast Clock / 2n IRCSCLK n=0-7 MCGOUTCLK MCGFLLCLK LOCRE0 LOCRE1 CME0 CME1 DRS External Clock Monitor LOCS0 DMX32 Filter DCO FLTPRSRV LOCS1 PLLS DCOOUT FLL FRDIV / 2n n=
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Chapter 24 Multipurpose Clock Generator (MCG) 24.1.2 Modes of Operation There are nine modes of operation for the MCG: FEI, FEE, FBI, FBE, PBE, PEE, BLPI, BLPE, and Stop. For details, see MCG modes of operation. 24.2 External Signal Description There are no MCG signals that connect off chip. 24.3 Memory Map/Register Definition This section includes the memory map and register definition. The MCG registers can only be written to when in supervisor mode.
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Memory Map/Register Definition 24.3.1 MCG Control 1 Register (MCG_C1) Address: MCG_C1 is 4006_4000h base + 0h offset = 4006_4000h Bit Read Write Reset 7 6 5 CLKS 0 4 3 FRDIV 0 0 0 0 2 1 0 IREFS IRCLKEN IREFSTEN 1 0 0 MCG_C1 field descriptions Field 7–6 CLKS Description Clock Source Select Selects the clock source for MCGOUTCLK . 00 01 10 11 5–3 FRDIV FLL External Reference Divider Selects the amount to divide down the external reference clock for the FLL.
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Chapter 24 Multipurpose Clock Generator (MCG) MCG_C1 field descriptions (continued) Field Description 0 1 0 IREFSTEN MCGIRCLK inactive. MCGIRCLK active. Internal Reference Stop Enable Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. 0 1 Internal reference clock is disabled in Stop mode. Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. 24.3.
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Memory Map/Register Definition MCG_C2 field descriptions (continued) Field Description Selects the source for the external reference clock. See the Oscillator (OSC) chapter for more details. 0 1 1 LP External reference clock requested. Oscillator requested. Low Power Select Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the MCG into BLPI mode.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.3.4 MCG Control 4 Register (MCG_C4) NOTE Reset values for DRST and DMX32 bits are 0. Address: MCG_C4 is 4006_4000h base + 3h offset = 4006_4003h Bit Read Write Reset 7 6 DMX32 5 4 3 DRST_DRS 0 0 2 1 FCTRIM 0 x* x* 0 SCFTRIM x* x* x* * Notes: • x = Undefined at reset. • A value for FCTRIM is loaded during reset from a factory programmed location . x = Undefined at reset.
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Memory Map/Register Definition MCG_C4 field descriptions (continued) Field Description The DRS bits select the frequency range for the FLL output, DCOOUT. When the LP bit is set, writes to the DRS bits are ignored. The DRST read field indicates the current frequency range for DCOOUT. The DRST field does not update immediately after a write to the DRS field due to internal synchronization between clock domains. See the DCO Frequency Range table for more details.
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Chapter 24 Multipurpose Clock Generator (MCG) MCG_C5 field descriptions (continued) Field Description 0 1 5 PLLSTEN0 MCGPLLCLK is active. PLL Stop Enable Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit has no affect and does not enable the PLL Clock to run if it is written to 1. 0 1 4–0 PRDIV0 MCGPLLCLK is inactive. MCGPLLCLK is disabled in any of the Stop modes.
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Memory Map/Register Definition MCG_C6 field descriptions Field 7 LOLIE0 Description Loss of Lock Interrrupt Enable Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect when LOLS 0 is set. 0 1 6 PLLS PLL Select Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.3.7 MCG Status Register (MCG_S) Address: MCG_S is 4006_4000h base + 6h offset = 4006_4006h Bit Read Write Reset 7 6 5 4 LOLS0 LOCK0 PLLST IREFST 3 0 0 0 1 2 CLKST 0 0 1 0 OSCINIT0 IRCST 0 0 MCG_S field descriptions Field 7 LOLS0 Description Loss of Lock Status This bit is a sticky bit indicating the lock status for the PLL.
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Memory Map/Register Definition MCG_S field descriptions (continued) Field 3–2 CLKST Description Clock Mode Status These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 01 10 11 1 OSCINIT0 0 IRCST Encoding 0 — Output of the FLL is selected (reset default). Encoding 1 — Internal reference clock is selected. Encoding 2 — External reference clock is selected.
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Chapter 24 Multipurpose Clock Generator (MCG) MCG_SC field descriptions (continued) Field 6 ATMS Description Automatic Trim Machine Select Selects the IRCS clock for Auto Trim Test. 0 1 5 ATMF Automatic Trim Machine Fail Flag Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC registers is detected or the MCG enters into any Stop mode. A write to ATMF clears the flag.
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Memory Map/Register Definition 24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH) Address: MCG_ATCVH is 4006_4000h base + Ah offset = 4006_400Ah Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 ATCVH 0 0 0 0 MCG_ATCVH field descriptions Field 7–0 ATCVH Description ATM Compare Value High Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 24.3.
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Chapter 24 Multipurpose Clock Generator (MCG) MCG_C7 field descriptions Field Description 7–1 Reserved This read-only field is reserved and always has the value zero. 0 OSCSEL MCG OSC Clock Select Selects the MCG FLL external reference clock 0 1 Selects System Oscillator (OSCCLK). Selects 32 kHz RTC Oscillator. 24.3.
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Functional Description MCG_C8 field descriptions (continued) Field Description 0 1 Loss of RTC has not occur. Loss of RTC has occur 24.4 Functional Description 24.4.1 MCG mode state diagram The nine states of the MCG are shown in the following figure and are described in Table 24-16. The arrows indicate the permitted MCG mode transitions.
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Chapter 24 Multipurpose Clock Generator (MCG) NOTE • During exits from LLS or VLPS when the MCG is in PEE mode, the MCG will reset to PBE clock mode and the C1[CLKS] and S[CLKST] will automatically be set to 2’b10. • If entering Normal Stop mode when the MCG is in PEE mode with C5[PLLSTEN]=0, the MCG will reset to PBE clock mode and C1[CLKS] and S[CLKST] will automatically be set to 2’b10. 24.4.1.1 MCG modes of operation The MCG operates in one of the following modes.
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Functional Description Table 24-16. MCG modes of operation (continued) Mode Description FLL Engaged External (FEE) FLL engaged external (FEE) mode is entered when all the following conditions occur: • C1[CLKS] bits are written to 00 • C1[IREFS] bit is written to 0 • C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.
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Chapter 24 Multipurpose Clock Generator (MCG) Table 24-16. MCG modes of operation (continued) Mode Description PLL Engaged External (PEE) PLL Engaged External (PEE) mode is entered when all the following conditions occur: • C1[CLKS] bits are written to 00 • C1[IREFS] bit is written to 0 • C6[PLLS] bit is written to 1 In PEE mode, the MCGOUTCLK is derived from the PLL clock, which is controlled by the external reference clock.
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Functional Description Table 24-16. MCG modes of operation (continued) Mode Description Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power mode assignments, see the chapter that describes how modules are configured and MCG behavior during Stop recovery.
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Chapter 24 Multipurpose Clock Generator (MCG) the FLL remains unlocked for several reference cycles. DCO startup time is equal to the FLL acquisition time. After the selected DCO startup time is over, the FLL is locked. The completion of the switch is shown by the C4[DRST_DRS] read bits. 24.4.2 Low Power Bit Usage The C2[LP] bit is provided to allow the FLL or PLL to be disabled and thus conserve power when these systems are not being used. The C4[DRST_DRS] can not be written while C2[LP] bit is 1.
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Functional Description 24.4.4 External Reference Clock The MCG module can support an external reference clock in all modes. See the device datasheet for external reference frequency range. When C1[IREFS] is set, the external reference clock will not be used by the FLL or PLL. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.4.6 MCG PLL clock The MCG PLL Clock (MCGPLLCLK) is available depending on the device's configuration of the MCG module. For more details, see the clock distribution chapter of this MCU. The MCGPLLCLK is prevented from coming out of the MCG until it is enabled and S[LOCK0] is set. 24.4.
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Initialization / Application information Before the ATM can be enabled, the ATM expected count needs to be derived and stored into the ATCV register.
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Chapter 24 Multipurpose Clock Generator (MCG) 2. Write to C1 register to select the clock mode. • If entering FEE mode, set C1[FRDIV] appropriately, clear the C1[IREFS] bit to switch to the external reference, and leave the C1[CLKS] bits at 2'b00 so that the output of the FLL is selected as the system clock source. • If entering FBE, clear the C1[IREFS] bit to switch to the external reference and change the C1[CLKS] bits to 2'b10 so that the external reference clock is selected as the system clock source.
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Initialization / Application information • When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24 MHz. • When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that can be achieved with a 32.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.5.2 Using a 32.768 kHz reference In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at low-range. If C4[DRST_DRS] bits are set to 2'b01, the multiplication factor is doubled to 1280, and the resulting DCO output frequency is 41.94 MHz at mid-low-range.
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Initialization / Application information Table 24-17.
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Chapter 24 Multipurpose Clock Generator (MCG) • C1[CLKS] set to 2'b10 to select external reference clock as system clock source • C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL • C1[IREFS] cleared to 0, selecting the external reference clock and enabling the external oscillator. c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by C2[EREFS0] has been initialized. d.
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Initialization / Application information e. PBE: Then loop until S[LOCK0] is set, indicating that the PLL has acquired lock. 4. Lastly, PBE mode transitions into PEE mode: a. C1 = 0x10 • C1[CLKS] set to 2'b00 to select the output of the PLL as the system clock source. b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode. • Now, with PRDIV0 of divide-by-2, and C6[VDIV0] of multiply-by-24, MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz.
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Chapter 24 Multipurpose Clock Generator (MCG) START IN FEI MODE C6 = 0x40 C2 = 0x1C IN BLPE MODE ? (S[LP]=1) C1 = 0x90 NO YES C2 = 0x1C (S[LP]=0) NO CHECK S[OSCINIT] = 1? CHECK S[PLLST] = 1? YES CHECK S[IREFST] = 0? NO YES NO CHECK S[LOCK] = 1? YES CHECK NO S[CLKST] = %10? NO YES C1 = 0x10 YES C5 = 0x01 (C5[VDIV] = 1) ENTER BLPE MODE ? CHECK S[CLKST] = %11? NO NO YES CONTINUE YES IN PEE MODE C2 = 0x1E (C2[LP] = 1) Figure 24-15.
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Initialization / Application information 24.5.3.2 Example 2: Moving from PEE to BLPI mode: MCGOUTCLK frequency =32 kHz In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence. 1. First, PEE must transition to PBE mode: a.
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Chapter 24 Multipurpose Clock Generator (MCG) • C1[IREFS] set to 1 to select the internal reference clock as the reference clock source. • C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference. b. Loop until S[IREFST] is 1, indicating the internal reference clock has been selected as the reference clock source. c. Loop until S[CLKST] are 2'b01, indicating that the internal reference clock is selected to feed MCGOUTCLK. 4. Lastly, FBI transitions into BLPI mode. a.
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Initialization / Application information START IN PEE MODE C1 = 0x90 CHECK S[PLLST] = 0? NO CHECK S[CLKST] = %10 ? YES C1 = 0x54 YES ENTER NO NO CHECK S[IREFST] = 0? BLPE MODE ? YES NO YES C2 = 0x1E (C2[LP] = 1) CHECK S[CLKST] = %01? NO C6 = 0x00 YES C2 = 0x02 IN BLPE MODE ? (C2[LP]=1) NO CONTINUE YES IN BLPI MODE C2 = 0x1C (C2[LP] = 0) Figure 24-16. Flowchart of PEE to BLPI mode transition using an 4 MHz crystal K20 Sub-Family Reference Manual, Rev.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.5.3.3 Example 3: Moving from BLPI to FEE mode In this example, the MCG will move through the proper operational modes from BLPI mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz MCGOUTCLK frequency. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence. 1. First, BLPI must transition to FBI mode. a.
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Initialization / Application information multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will switch back to 640. START IN BLPI MODE CHECK NO S[IREFST] = 0? C2 =0x00 YES C2 = 0x1C NO CHECK S[CLKST] = %00? C1 =0x10 YES CONTINUE CHECK S[OSCINIT] = 1 ? NO IN FEE MODE YES Figure 24-17. Flowchart of BLPI to FEE mode transition using an 4 MHz crystal K20 Sub-Family Reference Manual, Rev.
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Chapter 25 Oscillator (OSC) 25.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 25.
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Block Diagram 25.3 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals. Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode. OSCERCLK and OSC32KCLK can work in low power modes. For the clock source assignments, refer to the clock distribution information of this MCU.
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Chapter 25 Oscillator (OSC) Table 25-1. OSC Signal Descriptions Signal Description EXTAL External clock/Oscillator input I Oscillator output O XTAL I/O 25.5 External Crystal / Resonator Connections The connections for a crystal/resonator frequency reference are shown in the following figures. When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself.
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External Clock Connections OSC XTAL EXTAL VSS RF Crystal or Resonator Figure 25-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. OSC XTAL EXTAL VSS Cx Cy RF Crystal or Resonator Figure 25-4. Crystal/Ceramic Resonator Connections - Connection 3 25.6 External Clock Connections In external clock mode, the pins can be connected as shown below.
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Chapter 25 Oscillator (OSC) OSC XTAL EXTAL VSS Clock Input I/O Figure 25-5. External Clock Connections 25.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. 25.7.1 OSC Memory Map/Register Definition OSC memory map Absolute address (hex) 4006_5000 Width Access (in bits) Register name OSC Control Register (OSC0_CR) 8 R/W Reset value Section/ page 00h 25.71.1/ 471 25.71.
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Functional Description OSCx_CR field descriptions Field 7 ERCLKEN Description External Reference Enable Enables external reference clock (OSCERCLK). 0 1 6 Reserved 5 EREFSTEN This read-only field is reserved and always has the value zero. External Reference Stop Enable Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode. 0 1 4 Reserved 3 SC2P Oscillator 2 pF Capacitor Load Configure Configures the oscillator load. Configures the oscillator load.
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Chapter 25 Oscillator (OSC) 25.8.1 OSC Module States The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section.
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Functional Description 25.8.1.2 Oscillator Start-Up The OSC enters start-up state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized. When the oscillation amplitude becomes large enough to pass through the input buffer, XTL_CLK begins clocking the counter.
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Chapter 25 Oscillator (OSC) Table 25-7. Oscillator Modes Mode Frequency Range Low-frequency, high-gain fosc_lo (1 kHz) up to fosc_lo (32.
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Reset 25.8.2.3 High-Frequency, High-Gain Mode In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used. 25.8.2.
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Chapter 25 Oscillator (OSC) 25.10 Low Power Modes Operation When the MCU enters Stop modes, the OSC is functional depending on ERCLKEN and EREFSETN bit settings. If both these bits are set, the OSC is in operation. In Low Leakage Stop (LLS) modes, the OSC holds all register settings. If ERCLKEN and EREFSTEN bits are set before entry to Low Leakage Stop modes, the OSC is still functional in these modes.
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Interrupts K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 478 Freescale Semiconductor, Inc.
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Chapter 26 RTC Oscillator 26.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The RTC oscillator module provides the clock source for the RTC. The RTC oscillator module, in conjunction with an external crystal, generates a reference clock for the RTC. 26.1.
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RTC Signal Descriptions control Amplitude detector clk out for RTC EXTAL32 gm Rf XTAL32 C2 C1 PAD PAD Figure 26-1. RTC Oscillator Block Diagram 26.2 RTC Signal Descriptions The following table shows the user-accessible signals available for the RTC oscillator. See the chip-level specification to find out which signals are actually connected to the external pins. Table 26-1. RTC Signal Descriptions Signal EXTAL32 XTAL32 Description I/O Oscillator Input I Oscillator Output O 26.2.
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Chapter 26 RTC Oscillator 26.3 External Crystal Connections The connections with a crystal is shown in the following figure. External load capacitors and feedback resistor are not required. RTC Oscillator Module XTAL32 VSS EXTAL32 Crystal or Resonator Figure 26-2. Crystal Connections 26.4 Memory Map/Register Descriptions RTC oscillator control bits are part of the RTC registers. Refer to RTC_CR for more details. 26.
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Reset Overview 26.6 Reset Overview There is no reset state associated with the RTC oscillator. 26.7 Interrupts The RTC oscillator does not generate any interrupts. K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 482 Freescale Semiconductor, Inc.
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Chapter 27 Flash Memory Controller (FMC) 27.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Flash Memory Controller (FMC) is a memory acceleration unit that provides: • an interface between the device and the program flash memory and FlexNVM. • buffers that can accelerate flash memory and FlexNVM data transfers. 27.1.1 Overview The Flash Memory Controller manages the interface between the device and the flash memory.
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Modes of operation 27.1.2 Features The FMC's features include: • Interface between the device and the flash memory and FlexMemory: • 8-bit, 16-bit, and 32-bit read operations to program flash memory and FlexNVM used as data flash memory. • 8-bit, 16-bit, and 32-bit read and write operations to FlexNVM and FlexRAM used as EEPROM. • Read accesses to consecutive 32-bit spaces in memory return the second read data with no wait states. The memory returns 32 bits via the 32-bit bus access.
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Chapter 27 Flash Memory Controller (FMC) 27.4 Memory map and register descriptions The programming model consists of the FMC control registers and the program visible cache (data and tag/valid entries). NOTE Program the registers only while the flash controller is idle (for example, execute from RAM). Changing configuration settings while a flash access is in progress can lead to non-deterministic behavior. Table 27-2.
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Memory map and register descriptions Table 27-3. Program visible cache registers Cache storage Based at offset Contents of 32-bit read Nomenclature Nomenclature example Tag 100h 13'h0, tag[18:6], 5'h0, valid In TAGVDWxSy, x denotes the way, TAGVDW1S1 is the 13-bit and y denotes the set. tag and 1-bit valid for cache entry way 1, set 1. Data 200h Data word In DATAWxSy, x denotes the way, and y denotes the set. DATAW1S1 represents bits [31:0] of data entry way 1, set 1.
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Chapter 27 Flash Memory Controller (FMC) 27.4.
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Memory map and register descriptions FMC_PFAPR field descriptions (continued) Field Description 15–8 Reserved This field is reserved. 7–6 M3AP[1:0] Master 3 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master.
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Chapter 27 Flash Memory Controller (FMC) 27.4.
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Memory map and register descriptions FMC_PFB0CR field descriptions (continued) Field Description 0 1 19 S_B_INV Invalidate Prefetch Speculation Buffer This bit determines if the FMC's prefetch speculation buffer and the single entry page buffer are to be invalidated (cleared). When this bit is written, the speculation buffer and single entry buffer are immediately cleared. This bit always reads as zero.
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Chapter 27 Flash Memory Controller (FMC) FMC_PFB0CR field descriptions (continued) Field Description 1 B0IPE Instruction Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction fetches. 0 1 0 B0SEBE Do not prefetch in response to instruction fetches. Enable prefetches in response to instruction fetches. Single Entry Buffer Enable This bit controls whether the single entry page buffer is enabled in response to flash read accesses.
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Memory map and register descriptions 27.4.4 Cache Tag Storage (FMC_TAGVDW1Sn) The 32-entry cache is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for the 2 sets (n=0-1) in way 1.
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Chapter 27 Flash Memory Controller (FMC) FMC_TAGVDW2Sn field descriptions Field Description 31–19 Reserved This read-only field is reserved and always has the value zero. 18–6 tag[18:6] 13-bit tag for cache entry 5–1 Reserved This read-only field is reserved and always has the value zero. 0 valid 1-bit valid for cache entry 27.4.6 Cache Tag Storage (FMC_TAGVDW3Sn) The 32-entry cache is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1.
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Memory map and register descriptions 27.4.7 Cache Data Storage (FMC_DATAW0Sn) The cache of eight 32-bit entries is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1. In DATAWxSy, x denotes the way, and y denotes the set. This section represents data for bits [31:0] of sets 0-1 in way 0.
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Chapter 27 Flash Memory Controller (FMC) 27.4.9 Cache Data Storage (FMC_DATAW2Sn) The cache of eight 32-bit entries is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1. In DATAWxSy, x denotes the way, and y denotes the set. This section represents data for bits [31:0] of sets 0-1 in way 2.
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Functional description 27.5 Functional description The FMC is a flash acceleration unit with flexible buffers for user configuration. Besides managing the interface between the device and the flash memory and FlexMemory, the FMC can be used to restrict access from crossbar switch masters and customize the cache and buffers to provide single-cycle system-clock data-access times.
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Chapter 28 Flash Memory Module (FTFL) 28.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter.
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Introduction states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. 28.1.1 Features The flash memory module includes the following features. NOTE See the device's Chip Configuration details for the exact amount of flash memory available on your device. 28.1.1.
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Chapter 28 Flash Memory Module (FTFL) 28.1.1.
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Introduction Interrupt Register access Program flash Status registers Memory controller Control registers To MCU's flash controller FlexNVM Data flash FlexRAM EEPROM backup Figure 28-1. Flash Block Diagram 28.1.3 Glossary Command write sequence — A series of MCU writes to the flash FCCOB register group that initiates and controls the execution of flash algorithms that are built into the flash memory module.
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Chapter 28 Flash Memory Module (FTFL) EEPROM backup data record — The EEPROM backup data record is comprised of a 2-bit status field, a 14-bit address field, and a 16-bit data field found in EEPROM backup data memory which is used by the EEPROM filing system. If the status field indicates a record is valid, the data field is mirrored in the FlexRAM at a location determined by the address field.
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External Signal Description NVM Special Mode — An NVM mode enabling external, off-chip access to the memory resources in the flash memory module. A reduced flash command set is available when the MCU is secured. See the Chip Configuration details for information on when this mode is used. Phrase — 64 bits of data with an aligned phrase having byte-address[2:0] = 000. Longword — 32 bits of data with an aligned longword having byte-address[1:0] = 00.
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Chapter 28 Flash Memory Module (FTFL) 28.3.1 Flash Configuration Field Description The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the flash memory module. Flash Configuration Field Byte Address Size (Bytes) Field Description 0x0_0400 - 0x0_0407 8 Backdoor Comparison Key.
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Memory Map and Registers 28.3.2.1 Program Once Field The Program Once Field in the program flash IFR provides 64 bytes of user data storage separate from the program flash main array. The user can program the Program Once Field one time only as there is no program flash IFR erase mechanism available to the user. The Program Once Field can be read any number of times.
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Chapter 28 Flash Memory Module (FTFL) Table 28-2. EEPROM Data Set Size Field Description Field Description 7-4 This read-only bitfield is reserved and must always be written as one. Reserved EEPROM Size — Encoding of the total available FlexRAM for EEPROM use. 3-0 NOTE: EEESIZE must be 0 bytes (1111b) when the FlexNVM partition code (FlexNVM Partition Code) is set to 'No EEPROM'.
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Memory Map and Registers Table 28-4. FlexNVM Partition Code Field Description Field 7-4 Description This read-only bitfield is reserved and must always be written as one. Reserved 3-0 DEPART FlexNVM Partition Code — Encoding of the data flash / EEPROM backup split within the FlexNVM memory block. FlexNVM memory not partitioned for data flash will be used to store EEPROM records.
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Chapter 28 Flash Memory Module (FTFL) FTFL memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_0000 Flash Status Register (FTFL_FSTAT) 8 R/W 00h 28.34.1/ 508 4002_0001 Flash Configuration Register (FTFL_FCNFG) 8 R/W 00h 28.34.2/ 509 4002_0002 Flash Security Register (FTFL_FSEC) 8 R Undefined 28.34.3/ 511 4002_0003 Flash Option Register (FTFL_FOPT) 8 R Undefined 28.34.
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Memory Map and Registers FTFL memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4002_0016 EEPROM Protection Register (FTFL_FEPROT) 8 R/W Undefined 28.34.7/ 516 4002_0017 Data Flash Protection Register (FTFL_FDPROT) 8 R/W Undefined 28.34.8/ 517 28.34.1 Flash Status Register (FTFL_FSTAT) The FSTAT register reports the operational status of the flash memory module. The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable.
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Chapter 28 Flash Memory Module (FTFL) FTFL_FSTAT field descriptions (continued) Field Description error by the block arbitration logic. The read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by writing a 1 to it. Writing a 0 to RDCOLERR has no effect. 0 1 5 ACCERR Flash Access Error Flag The ACCERR error bit indicates an illegal access has occurred to a flash memory resource caused by a violation of the command write sequence or issuing an illegal flash command.
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Memory Map and Registers Address: FTFL_FCNFG is 4002_0000h base + 1h offset = 4002_0001h Bit Read Write Reset 7 6 5 CCIE RDCOLLIE 0 0 ERSAREQ 0 4 ERSSUSP 0 3 2 1 0 0 PFLSH RAMRDY EEERDY 0 0 0 0 FTFL_FCNFG field descriptions Field 7 CCIE Description Command Complete Interrupt Enable The CCIE bit controls interrupt generation when a flash command completes.
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Chapter 28 Flash Memory Module (FTFL) FTFL_FCNFG field descriptions (continued) Field Description The state of the RAMRDY flag is normally controlled by the Set FlexRAM Function command. During the reset sequence, the RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and is set if the FlexNVM block is not partitioned for EEPROM. The RAMRDY flag is cleared if the Program Partition command is run to partition the FlexNVM block for EEPROM.
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Memory Map and Registers FTFL_FSEC field descriptions (continued) Field Description 01 10 11 5–4 MEEN Mass Erase Enable Bits Enables and disables mass erase capability of the flash memory module. The state of the MEEN bits is only relevant when the SEC bits are set to secure outside of NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does not matter.
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Chapter 28 Flash Memory Module (FTFL) During the reset sequence, the register is loaded from the flash nonvolatile option byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. Address: FTFL_FOPT is 4002_0000h base + 3h offset = 4002_0003h Bit Read Write Reset 7 6 5 4 3 2 1 0 x* x* x* x* OPT x* x* x* x* * Notes: • x = Undefined at reset.
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Memory Map and Registers FTFL_FCCOBn field descriptions (continued) Field Description The following table shows a generic flash command format. The first FCCOB register, FCCOB0, always contains the command code. This 8-bit value defines the command to be executed. The command code is followed by the parameters required for this specific flash command, typically an address and/or data values. NOTE: The command parameter table is written in terms of FCCOB Number (which is equivalent to the byte number).
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Chapter 28 Flash Memory Module (FTFL) Program flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the FPROT registers are loaded with the contents of the program flash protection bytes in the Flash Configuration Field as indicated in the following table.
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Memory Map and Registers FTFL_FPROTn field descriptions (continued) Field Description Trying to alter data in any protected area in the program flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible if it contains any protected region. Each bit in the 32-bit protection register represents 1/32 of the total program flash . 0 1 Program flash region is protected. Program flash region is not protected 28.34.
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Chapter 28 Flash Memory Module (FTFL) FTFL_FEPROT field descriptions (continued) Field Description Reset: During the reset sequence, the FEPROT register is loaded with the contents of the FlexRAM protection byte in the Flash Configuration Field located in program flash. The flash basis for the reset values is signified by X in the register diagram.
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Functional Description FTFL_FDPROT field descriptions (continued) Field Description Reset: During the reset sequence, the FDPROT register is loaded with the contents of the data flash protection byte in the Flash Configuration Field located in program flash memory. The flash basis for the reset values is signified by X in the register diagram.
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Chapter 28 Flash Memory Module (FTFL) • FDPROT — • protects eight regions of the data flash memory as shown in the following figure FlexNVM 0x0_0000 EEPROM backup size (DEPART) Last data flash address Data flash size / 8 DPROT0 Data flash size / 8 DPROT1 Data flash size / 8 DPROT2 Data flash size / 8 DPROT3 Data flash size / 8 DPROT4 Data flash size / 8 DPROT5 Data flash size / 8 DPROT6 Data flash size / 8 DPROT7 EEPROM backup Last FlexNVM address Figure 28-27.
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Functional Description FlexRAM EEPROM size (EEESIZE) 0x0_0000 Last EEPROM address EEPROM size / 8 EPROT0 EEPROM size / 8 EPROT1 EEPROM size / 8 EPROT2 EEPROM size / 8 EPROT3 EEPROM size / 8 EPROT4 EEPROM size / 8 EPROT5 EEPROM size / 8 EPROT6 EEPROM size / 8 EPROT7 Unavailable Last FlexRAM address Figure 28-28. EEPROM protection 28.4.2 FlexNVM Description This section describes the FlexNVM memory. 28.4.2.
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Chapter 28 Flash Memory Module (FTFL) CAUTION While different partitions of the FlexNVM block are available, the intention is that a single partition choice is used throughout the entire lifetime of a given application. The FlexNVM partition code choices affect the endurance and data retention characteristics of the device. 28.4.2.2 EEPROM User Perspective The EEPROM system is shown in the following figure.
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Functional Description Data flash memory is useful for applications that need to quickly store large amounts of data or store data that is static. The EEPROM partition in FlexRAM is useful for storing smaller amounts of data that will be changed often. FlexNVM EEESIZE FlexRAM FlexRAM base address DEPART FlexNVM base address Data flash EEPROM partition Unavailable EEPROM backup Figure 28-30. FlexRAM to FlexNVM Memory Mapping 28.4.2.
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Chapter 28 Flash Memory Module (FTFL) After a sector in EEPROM backup is full of EEPROM data records, EEPROM data records from the sector holding the oldest data are gradually copied over to a previouslyerased EEPROM backup sector. When the sector copy completes, the EEPROM backup sector holding the oldest data is tagged for erase. 28.4.2.
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Functional Description Figure 28-31. EEPROM backup writes to FlexRAM 28.4.3 Interrupts The flash memory module can generate interrupt requests to the MCU upon the occurrence of various flash events. These interrupt events and their associated status and control bits are shown in the following table. Table 28-30.
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Chapter 28 Flash Memory Module (FTFL) 28.4.4 Flash Operation in Low-Power Modes 28.4.4.1 Wait Mode When the MCU enters wait mode, the flash memory module is not affected. The flash memory module can recover the MCU from wait via the command complete interrupt (see Interrupts). 28.4.4.2 Stop Mode When the MCU requests stop mode, if a flash command is active (CCIF = 0) the command execution completes before the MCU is allowed to enter stop mode.
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Flash Operation in Low-Power Modes 28.4.7 Read While Write (RWW) The following simultaneous accesses are allowed: • The user may read from the program flash memory while commands (typically program and erase operations) are active in the data flash and FlexRAM memory space. • The MCU can fetch instructions from program flash during both data flash program and erase operations and while EEPROM backup data is maintained by the EEPROM commands.
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Chapter 28 Flash Memory Module (FTFL) 28.4.9.1 Command Write Sequence Flash commands are specified using a command write sequence illustrated in Figure 28-32. The flash memory module performs various checks on the command (FCCOB) content and continues with command execution if all requirements are fulfilled. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be zero and the CCIF flag must read 1 to verify that any previous command has completed.
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Flash Operation in Low-Power Modes Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails, the FSTAT[FPVIOL] (protection error) flag is set. Command processing never proceeds to execution when the parameter or protection step fails. Instead, command processing is terminated after setting the FSTAT[CCIF] bit. 2. If the parameter and protection checks pass, the command proceeds to execution.
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Chapter 28 Flash Memory Module (FTFL) START Read: FSTAT register FCCOB Availability Check no CCIF = ‘1’? Previous command complete? yes Access Error and Protection Violation Check Results from previous command yes ACCERR/ FPVIOL Set? Clear the old errors Write 0x30 to FSTAT register no Write to the FCCOB registers to load the required command parameter. More Parameters? yes no Clear the CCIF to launch the command Write 0x80 to FSTAT register EXIT Figure 28-32.
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Flash Operation in Low-Power Modes FCMD Command Program flash Data flash 0x01 Read 1s Section × × FlexRAM Verify that a given number of program flash or data flash locations from a starting address are erased. 0x02 Program Check × × Tests previouslyprogrammed locations at margin read levels. 0x03 Read Resource IFR, ID IFR Read 4 bytes from program flash IFR, data flash IFR, or version ID. 0x06 Program Longword × × Program 4 bytes in a program flash block or a data flash block.
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Chapter 28 Flash Memory Module (FTFL) FCMD Command Program flash 0x43 Program Once IFR 0x44 Erase All Blocks × Data flash FlexRAM Function One-time program of 4 bytes of a dedicated 64-byte field in the program flash IFR. × × Erase all program flash blocks, data flash blocks, FlexRAM, EEPROM backup data records, and data flash IFR. Then, verify-erase and release MCU security. NOTE: × An erase is only possible when all memory locations are unprotected.
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Flash Operation in Low-Power Modes 28.4.9.3 Flash Commands by Mode The following table shows the flash commands that can be executed in each flash operating mode. Table 28-31.
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Chapter 28 Flash Memory Module (FTFL) Table 28-32. Allowed Simultaneous Memory Operations Program Flash Read Read Read OK Program OK Sector Erase OK Read FlexRAM Program Sector Erase OK OK R-Write2 OK OK3 — OK OK OK OK — OK OK — OK OK OK — OK OK OK R-Write2 E-Write1 OK — OK Read OK — Read FlexRAM E-Write1 Sector Erase — Program Program flash Sector Erase Data flash Program Data Flash — OK OK OK OK — 1.
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Flash Operation in Low-Power Modes The 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads have at least this much safety margin before they experience data loss. The 'user' margin is a small delta to the normal read reference level. 'User' margin levels can be employed to check that flash memory contents have adequate margin for normal level read operations.
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Chapter 28 Flash Memory Module (FTFL) • program flash (=0) block • data flash (=1) block CAUTION Flash data must be in the erased state before being programmed. Cumulative programming of bits (adding more zeros) is not allowed. 28.4.11.1 Read 1s Block Command The Read 1s Block command checks to see if an entire program flash or data flash block has been erased to the specified margin level. The FCCOB flash address bits determine which logical block is erase-verified. Table 28-33.
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Flash Operation in Low-Power Modes Table 28-35.
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Chapter 28 Flash Memory Module (FTFL) Table 28-38. Read 1s Section Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin code is supplied FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] The requested section crosses a Flash block boundary FSTAT[ACCERR] The requested number of longwords is zero FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] 28.4.11.
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Flash Operation in Low-Power Modes • Byte 1 data is expected at byte address start + 0b01, • Byte 2 data is expected at byte address start + 0b10, and • Byte 3 data is expected at byte address start + 0b11. NOTE See the description of margin reads, Margin Read Commands Table 28-40. Margin Level Choices for Program Check Read Margin Choice Margin Level Description 0x01 Read at 'User' margin-1 and 'User' margin-0 0x02 Read at 'Factory' margin-1 and 'Factory' margin-0 Table 28-41.
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Chapter 28 Flash Memory Module (FTFL) Table 28-42. Read Resource Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] User-provided values 8 Resource Select Code (see Table 28-43) 1. Must be longword aligned (Flash address [1:0] = 00). Table 28-43. Read Resource Select Codes Resource Select Code1 Description Resource Size Local Address Range 0x00 IFR 256 Bytes 0x0000 - 0x00FF 0x012 Version ID 8 Bytes 0x0000 - 0x0007 1.
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Flash Operation in Low-Power Modes Table 28-45. Program Longword Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x06 (PGM4) 1 Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0]1 4 Byte 0 program value 5 Byte 1 program value 6 Byte 2 program value 7 Byte 3 program value 1. Must be longword aligned (Flash address [1:0] = 00).
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Chapter 28 Flash Memory Module (FTFL) 28.4.11.6 Erase Flash Block Command The Erase Flash Block operation erases all addresses in a single program flash or data flash block. Table 28-47. Erase Flash Block Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x08 (ERSBLK) 1 Flash address [23:16] in the flash block to be erased 2 Flash address [15:8] in the flash block to be erased 3 Flash address [7:0]1 in the flash block to be erased 1.
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Flash Operation in Low-Power Modes Table 28-49. Erase Flash Sector Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] 1 Flash address [23:16] in the flash sector to be erased 2 Flash address [15:8] in the flash sector to be erased 3 Flash address [7:0]1 in the flash sector to be erased 1. Must be longword aligned (flash address [1:0] = 00).
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Chapter 28 Flash Memory Module (FTFL) 28.4.11.7.2 Resuming a Suspended Erase Flash Sector Operation If the ERSSUSP bit is still set when CCIF is cleared to launch the next command, the previous Erase Flash Sector operation resumes. The flash memory module acknowledges the request to resume a suspended operation by clearing the ERSSUSP bit. A new suspend request can then be made by setting ERSSUSP. A single Erase Flash Sector operation can be suspended and resumed multiple times.
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Flash Operation in Low-Power Modes Enter with CCIF = 1 Command Initiation ERSSCR Command (Write FCCOB) Memory Controller Command Processing Launch/Resume Command (Clear CCIF) Yes SUSPACK=1 Next Command (Write FCCOB) Yes CCIF = 1? No No Interrupt? Yes Request Suspend (Set ERSSUSP) Start New No Restore Erase Algo Clear SUSPACK = 0 Execute Yes DONE? No ERSSUSP=1? No CCIF = 1? Resume ERSSCR No Yes Save Erase Algo Clear ERSSUSP Yes Service Interrupt (Read Flash) ERSSCR Suspended ERSSUSP=1
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Chapter 28 Flash Memory Module (FTFL) 28.4.11.8 Program Section Command The Program Section operation programs the data found in the section program buffer to previously erased locations in the flash memory using an embedded algorithm. Data is preloaded into the section program buffer by writing to the FlexRAM while it is set to function as traditional RAM (see Flash Sector Programming). The section program buffer is limited to the lower half of the RAM.
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Flash Operation in Low-Power Modes Table 28-52.
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Chapter 28 Flash Memory Module (FTFL) 28.4.11.9 Read 1s All Blocks Command The Read 1s All Blocks command checks if the program flash blocks, data flash blocks, EEPROM backup records, and data flash IFR have been erased to the specified read margin level, if applicable, and releases security if the readout passes, i.e. all data reads as '1'. Table 28-53.
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Flash Operation in Low-Power Modes 28.4.11.10 Read Once Command The Read Once command provides read access to a reserved 64-byte field located in the program flash IFR (see Program Flash IFR Map and Program Once Field). Access to this field is via 16 records, each 4 bytes long. The Read Once field is programmed using the Program Once command described in Program Once Command. Table 28-56.
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Chapter 28 Flash Memory Module (FTFL) Table 28-58. Program Once Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x43 (PGMONCE) 1 Program Once record index (0x00 - 0x0F) 2 Not Used 3 Not Used 4 Program Once Byte 0 value 5 Program Once Byte 1 value 6 Program Once Byte 2 value 7 Program Once Byte 3 value After clearing CCIF to launch the Program Once command, the flash memory module first verifies that the selected record is erased.
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Flash Operation in Low-Power Modes After clearing CCIF to launch the Erase All Blocks command, the flash memory module erases all program flash memory, data flash memory, data flash IFR space, EEPROM backup memory, and FlexRAM, then verifies that all are erased. If the flash memory module verifies that all flash memories and the FlexRAM were properly erased, security is released by setting the FSEC[SEC] field to the unsecure state and the FCNFG[RAMRDY] bit is set.
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Chapter 28 Flash Memory Module (FTFL) FCCOB match those stored in the Backdoor Comparison Key bytes of the Flash Configuration Field (see Flash Configuration Field Description). The column labelled Flash Configuration Field offset address shows the location of the matching byte in the Flash Configuration Field. Table 28-62.
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Flash Operation in Low-Power Modes 28.4.11.14 Program Partition Command The Program Partition command prepares the FlexNVM block for use as data flash, EEPROM backup, or a combination of both and initializes the FlexRAM. The Program Partition command must not be launched from flash memory, since flash memory resources are not accessible during Program Partition command execution.
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Chapter 28 Flash Memory Module (FTFL) Table 28-66. Valid FlexNVM Partition Codes FlexNVM Partition Code (FCCOB5[DEPART])1 Data flash Size (Kbytes) EEPROM backup Size (Kbytes) 0000 32 0 0001 24 8 0010 16 16 0011 0 32 1000 0 32 1001 8 24 1010 16 16 1011 32 0 1. FCCOB5[7:4] = 0000 After clearing CCIF to launch the Program Partition command, the flash memory module first verifies that the EEPROM Data Size Code and FlexNVM Partition Code in the data flash IFR are erased.
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Flash Operation in Low-Power Modes Table 28-67. Program Partition Command Error Handling (continued) Error Condition Error Bit FCCOB5[7:4] != 0000 FSTAT[ACCERR] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 28.4.11.15 Set FlexRAM Function Command The Set FlexRAM Function command changes the function of the FlexRAM: • When not partitioned for EEPROM, the FlexRAM is typically used as traditional RAM.
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Chapter 28 Flash Memory Module (FTFL) flash memory need to be programmed, e.g. during factory programming, the FlexRAM can be used as the Section Program Buffer for the Program Section command (see Program Section Command).
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Flash Operation in Low-Power Modes 28.4.12.1 Flash Memory Access by Mode and Security The following table summarizes how access to the flash memory module is affected by security and operating mode. Table 28-72. Flash Memory Access Summary Operating Mode Chip Security State Unsecure NVM Normal NVM Special Secure Full command set Full command set Only the Erase All Blocks and Read 1s All Blocks commands. 28.4.12.
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Chapter 28 Flash Memory Module (FTFL) 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Verify Backdoor Access Key Command 2. If the Verify Backdoor Access Key command is successful, the chip is unsecured and the FSEC[SEC] bits are forced to the unsecure state An illegal key provided to the Verify Backdoor Access Key command prohibits further use of the Verify Backdoor Access Key command.
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Flash Operation in Low-Power Modes K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 558 Freescale Semiconductor, Inc.
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Chapter 29 EzPort 29.1 Overview NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The EzPort module is a serial flash programming interface that allows In-System Programming (ISP) of flash memory contents on a 32 bit general-purpose microcontroller.
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Overview EzPort Enabled G EZP_CS EZP_CK Flash Controller EzPort EZP_D EZP_Q Reset Flash Memory Reset Out Reset Controller Microcontroller Core Figure 29-1. EzPort block diagram 29.1.2 Features EzPort includes the following features: • Serial interface that is compatible with a subset of the SPI format. • Ability to read, erase, and program flash memory. • Ability to reset the microcontroller, allowing it to boot from the flash memory after the memory has been configured. 29.1.
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Chapter 29 EzPort The EzPort provides a simple interface to connect an external device to the flash memory on board a 32 bit microcontroller. The interface itself is compatible with the SPI interface, with the EzPort operating as a slave, running in either of the two following modes. The data is transmitted with the most significant bit first. • CPOL = 0, CPHA = 0 • CPOL = 1, CPHA = 1 Commands are issued by the external device to erase, program, or read the contents of the flash memory.
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Command definition 29.2.2 EzPort Chip Select (EZP_CS) EZP_CS is the chip select for signaling the start and end of serial transfers. If, while EZP_CS is asserted, the microcontroller's reset out signal is negated, EzPort is enabled out of reset; otherwise it is disabled. After EzPort is enabled, asserting EZP_CS commences a serial data transfer, which continues until EZP_CS is negated again.
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Chapter 29 EzPort Table 29-2. EzPort commands (continued) Command Description Code Address Bytes Data Bytes Accepted when secure? RESET Reset Chip 0xB9 0 0 Yes WRFCCOB Write FCCOB Registers 0xBA 0 12 Yes6 FAST_RDFCCOB Read FCCOB registers at high speed 0xBB 0 1 - 122 No WRFLEXRAM Write FlexRAM 0xBC 31 4 No RDFLEXRAM Read FlexRAM 0xBD 31 1+ No 0xBE 31 1+2 No FAST_RDFLEXRAM Read FlexRAM at high speed 1. 2. 3. 4.
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Command definition Table 29-3. EzPort status register R 7 6 FS WEF 0/11 0 5 4 3 2 1 0 FLEXRAM BEDIS WEN WIP 0/12 0/13 0 14 W Reset: 0 0 1. Reset value reflects the status of flash security out of reset. 2. Reset value reflects FlexNVM flash partitioning. If FlexNVM flash has been paritioned for EEPROM, this field is set immediately after reset. Note that FLEXRAM is cleared after the EzPort initialization sequence completes, as indicated by clearing of WIP. 3.
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Chapter 29 EzPort Table 29-4. EzPort status register field description (continued) Field Description 6 Write error flag WEF Indicates whether there has been an error while executing a write command (SP, SE, BE, WRFCCOB, or WRFLEXRAM). The WEF flag will set if Flash Access Error Flag (ACCERR), Flash Protection Violation (FPVIOL), or Memory Controller Command Completion Status (MGSTAT0) inside the flash memory is set at the completion of the write command.
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Command definition 29.3.1.6 Section Program The Section Program (SP) command programs up to one section of flash memory that has previously been erased. A section is defined as the smaller of the flash sector size or half the size of the FlexRAM. The starting address of the memory to program is sent after the command word and must be a 64-bit aligned address with the three LSBs being zero). As data is shifted in, the EzPort buffers the data in FlexRAM before executing an SP command within the flash.
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Chapter 29 EzPort 29.3.1.8 Bulk Erase The Bulk Erase (BE) command erases the entire contents of flash memory, ignoring any protected sectors or flash security. Flash security is disabled upon successful completion of the BE command. Attempts to issue a BE command while the BEDIS and FS fields are set results in the WEF flag being set in the EzPort status register. Also, this command is not accepted if the WEF or WIP field is set or if the WEN field is not set in the EzPort status register. 29.3.1.
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Command definition 29.3.1.11 Read FCCOB Registers at High Speed The Read FCCOB Registers at High Speed (FAST_RDFCCOB) command allows the user to read the contents of the flash common command object registers. After receiving the command, EzPort waits for one dummy byte of data before returning FCCOB register data starting at FCCOB 0 and ending with FCCOB B. This command can be run with an EzPort clock (EZP_CK) frequency half the internal system clock frequency of the microcontroller or slower.
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Chapter 29 EzPort Data continues being returned for as long as the EzPort chip select (EZP_CS) is asserted, with the address automatically incrementing. In this way, the entire contents of FlexRAM can be returned by one command. The initial address must be 32-bit aligned (the two LSBs must be zero). Attempts to read from an address which does not fall within the valid address range for the FlexRAM returns unknown data. See Flash memory map for EzPort access for more information.
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Flash memory map for EzPort access K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 570 Freescale Semiconductor, Inc.
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Chapter 30 Cyclic Redundancy Check (CRC) 30.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The cyclic redundancy check (CRC) module generates 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. The 16/32-bit code is calculated for 32 bits of data at a time. 30.1.
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Memory map and register descriptions 30.1.2 Block diagram The following is a block diagram of the CRC. TOT WAS FXOR NOT Logic CRC Data Checksum CRC Polynomial Register [31:24] [23:16] [15:8] [7:0] TOTR Seed Reverse Logic MUX CRC Data Register [31:24] [23:16] [15:8] [7:0] Reverse Logic CRC Data Register [31:24] [23:16] [15:8] [7:0] CRC Engine Data Combine Logic Polynomial 16-/32-bit Select TCRC Figure 30-1. Programmable cyclic redundancy check (CRC) block diagram 30.1.
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Chapter 30 Cyclic Redundancy Check (CRC) CRC memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4003_2000 CRC Data register (CRC_CRC) 32 R/W FFFF_ FFFFh 30.2.1/ 573 4003_2004 CRC Polynomial register (CRC_GPOLY) 32 R/W 0000_1021h 30.2.2/ 574 4003_2008 CRC Control register (CRC_CTRL) 32 R/W 0000_0000h 30.2.3/ 575 30.2.1 CRC Data register (CRC_CRC) The CRC Data register contains the value of the seed, data, and checksum.
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Memory map and register descriptions CRC_CRC field descriptions (continued) Field Description 23–16 HL CRC High Lower Byte 15–8 LU CRC Low Upper Byte 7–0 LL CRC Low Lower Byte In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data written to this field is used for CRC checksum generation in both 16-bit and 32-bit CRC modes.
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Chapter 30 Cyclic Redundancy Check (CRC) 30.2.3 CRC Control register (CRC_CTRL) This register controls the configuration and working of the CRC module. Appropriate bits must be set before starting a new CRC calculation. A new CRC calculation is initialized by asserting CTRL[WAS] and then writing the seed into the CRC data register.
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Functional description CRC_CTRL field descriptions (continued) Field Description 0 1 24 TCRC 23–0 Reserved Writes to the CRC data register are data values. Writes to the CRC data register are seed values. Width of CRC protocol. 0 1 16-bit CRC protocol. 32-bit CRC protocol. This read-only field is reserved and always has the value zero. 30.3 Functional description 30.3.
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Chapter 30 Cyclic Redundancy Check (CRC) 3. Write a 16-bit polynomial to the GPOLY[LOW] field. The GPOLY[HIGH] field is not usable in 16-bit CRC mode. 4. Set CTRL[WAS] to program the seed value. 5. Write a 16-bit seed to CRC[LU:LL]. CRC[HU:HL] are not used. 6. Clear CTRL[WAS] to start writing data values. 7. Write data values into CRC[HU:HL:LU:LL]. A CRC is computed on every data value write, and the intermediate CRC result is stored back into CRC[LU:LL]. 8.
PAGE 578
Functional description Some protocols use little endian format for the data stream to calculate a CRC. In this case, the transpose feature usefully flips the bits. This transpose option is one of the types supported by the CRC module. 30.3.3.1 Types of transpose The CRC module provides several types of transpose functions to flip the bits and/or bytes, for both writing input data and reading the CRC result, separately using the CTRL[TOT] or CTRL[TOTR] fields, according to the CRC calculation being used.
PAGE 579
Chapter 30 Cyclic Redundancy Check (CRC) Bytes are transposed, but bits are not transposed. reg[31:0] becomes {reg[7:0], reg[15:8], reg[23:16], reg[31:24]} 31 7 24 23 16 15 8 0 15 8 23 16 7 31 0 24 Figure 30-7. Transpose type 11 NOTE For 8-bit and 16-bit write accesses to the CRC data register, the data is transposed with zeros on the unused byte or bytes (taking 32 bits as a whole), but the CRC is calculated on the valid byte(s) only.
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Functional description K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 580 Freescale Semiconductor, Inc.
PAGE 581
Chapter 31 Analog-to-Digital Converter (ADC) 31.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The 16-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE For the chip specific modes of operation, refer to the Power Management information for the device. 31.1.
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Introduction • Input clock selectable from up to four sources • Operation in low power modes for lower noise operation • Asynchronous clock source for lower noise operation with option to output the clock • Selectable hardware conversion trigger with hardware channel select • Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value • Temperature sensor • Hardware average function • Selectable voltage reference: external or alternate • Self-
PAGE 583
Chapter 31 Analog-to-Digital Converter (ADC) ADHWTSA SC1A Conversion Trigger Control ADHWTSn ADHWT SC1n ADTRG Control Registers (SC2, CFG1, CFG2) Async Clock Gen A D IC L K A D IV ADLPC/ADHSC MODE ADLSMP/ADLSTS DIFF ADCO trig g e r ADACKEN c o m p le te AIEN COCO ADCH C o m p a re tru e 1 Interrupt MCU STOP Control Sequencer ADCK ADACK Clock Divide Bus Clock 2 AD23 TempP ALTCLK abort transfer convert DADP3 AD4 sample initialize DADP0 A D V IN P PG, MG A D V IN M CLPx SAR
PAGE 584
ADC Signal Descriptions Table 31-1. ADC Signal Descriptions (continued) Signal DADM[3:0] Description I/O Differential analog channel inputs I Single-ended analog channel inputs I VREFSH Voltage reference select high I VREFSL Voltage reference select low I VDDA Analog power supply I VSSA Analog ground I AD[23:4] 31.2.1 Analog power (VDDA) The ADC analog portion uses VDDA as its power connection. In some packages, VDDA is connected internally to VDD.
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Chapter 31 Analog-to-Digital Converter (ADC) In some packages, VREFH is connected in the package to VDDA and VREFL to VSSA. If externally available, the positive reference(s) may be connected to the same potential as VDDA or may be driven by an external source to a level between the minimum Ref Voltage High and the VDDA potential (VREFH must never exceed VDDA). Connect the ground references to the same voltage potential as VSSA. 31.2.
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Register Definition ADC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_B00C Configuration register 2 (ADC0_CFG2) 32 R/W 0000_0000h 31.3.3/ 592 4003_B010 ADC data result register (ADC0_RA) 32 R 0000_0000h 31.3.4/ 593 4003_B014 ADC data result register (ADC0_RB) 32 R 0000_0000h 31.3.4/ 593 4003_B018 Compare value registers (ADC0_CV1) 32 R/W 0000_0000h 31.3.
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Chapter 31 Analog-to-Digital Converter (ADC) ADC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_B060 ADC minus-side general calibration value register (ADC0_CLM3) 32 R/W 0000_0100h 31.3.21/ 605 4003_B064 ADC minus-side general calibration value register (ADC0_CLM2) 32 R/W 0000_0080h 31.3.22/ 606 4003_B068 ADC minus-side general calibration value register (ADC0_CLM1) 32 R/W 0000_0040h 31.3.
PAGE 588
Register Definition Addresses: ADC0_SC1A is 4003_B000h base + 0h offset = 4003_B000h ADC0_SC1B is 4003_B000h base + 4h offset = 4003_B004h Bit 31 30 29 28 27 26 25 24 0 0 0 0 19 18 17 16 0 0 0 0 11 10 9 8 0 R W Reset 0 0 0 0 Bit 23 22 21 20 0 R W Reset 0 0 0 0 Bit 15 14 13 12 0 R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 R COCO AIEN DIFF 0 0 1 1 W Reset 0 ADCH 1 1 1 ADCx_SC1n field descriptions Field 31–8 Reserved 7 COCO D
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Chapter 31 Analog-to-Digital Converter (ADC) ADCx_SC1n field descriptions (continued) Field Description 0 1 4–0 ADCH Single-ended conversions and input channels are selected. Differential conversions and input channels are selected. Input channel select The ADCH bits form a 5-bit field that selects one of the input channels. The input channel decode depends on the value of the DIFF bit. DAD0-DAD3 are associated with the input pin pairs DADPx and DADMx.
PAGE 590
Register Definition 31.3.2 ADC configuration register 1 (ADCx_CFG1) CFG1 register selects the mode of operation, clock source, clock divide, and configure for low power or long sample time.
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Chapter 31 Analog-to-Digital Converter (ADC) ADCx_CFG1 field descriptions (continued) Field Description speed for lower impedance inputs. Longer sample times can also be used to lower overall power consumption if continuous conversions are enabled and high conversion rates are not required. When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the extent of the long sample time. 0 1 3–2 MODE Conversion mode selection MODE bits are used to select the ADC resolution mode.
PAGE 592
Register Definition 31.3.3 Configuration register 2 (ADCx_CFG2) CFG2 register selects the special high speed configuration for very high speed conversions and selects the long sample time duration during long sample mode.
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Chapter 31 Analog-to-Digital Converter (ADC) ADCx_CFG2 field descriptions (continued) Field Description 0 1 2 ADHSC High speed configuration ADHSC configures the ADC for very high speed operation. The conversion sequence is altered (2 ADCK cycles added to the conversion time) to allow higher speed conversion clocks. 0 1 1–0 ADLSTS Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.
PAGE 594
Register Definition Table 31-43.
PAGE 595
Chapter 31 Analog-to-Digital Converter (ADC) The compare value 2 register (CV2) is utilized only when the compare range function is enabled (ACREN=1).
PAGE 596
Register Definition ADCx_SC2 field descriptions Field 31–8 Reserved 7 ADACT Description This read-only field is reserved and always has the value zero. Conversion active ADACT indicates that a conversion or hardware averaging is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted. 0 1 6 ADTRG Conversion trigger select ADTRG selects the type of trigger used for initiating a conversion.
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Chapter 31 Analog-to-Digital Converter (ADC) ADCx_SC2 field descriptions (continued) Field Description 00 01 10 11 Default voltage reference pin pair (external pins VREFH and VREFL) Alternate reference pair (VALTH and VALTL). This pair may be additional external pins or internal sources depending on MCU configuration. Consult the Chip Configuration information for details specific to this MCU. Reserved Reserved 31.3.
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Register Definition ADCx_SC3 field descriptions (continued) Field Description 5–4 Reserved This read-only field is reserved and always has the value zero. 3 ADCO Continuous conversion enable ADCO enables continuous conversions. 0 1 2 AVGE One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
PAGE 599
Chapter 31 Analog-to-Digital Converter (ADC) ADCx_OFS field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. 15–0 OFS Offset error correction value 31.3.9 ADC plus-side gain register (ADCx_PG) The plus-side gain register (PG) contains the gain error correction for the plus-side input in differential mode or the overall conversion in single-ended mode.
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Register Definition Addresses: ADC0_MG is 4003_B000h base + 30h offset = 4003_B030h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 MG W Reset 8 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 ADCx_MG field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. 15–0 MG Minus-side gain 31.3.
PAGE 601
Chapter 31 Analog-to-Digital Converter (ADC) 31.3.12 ADC plus-side general calibration value register (ADCx_CLPS) For more information, refer to CLPD register description.
PAGE 602
Register Definition 31.3.14 ADC plus-side general calibration value register (ADCx_CLP3) For more information, refer to CLPD register description.
PAGE 603
Chapter 31 Analog-to-Digital Converter (ADC) 31.3.16 ADC plus-side general calibration value register (ADCx_CLP1) For more information, refer to CLPD register description.
PAGE 604
Register Definition 31.3.18 ADC minus-side general calibration value register (ADCx_CLMD) CLMx contain calibration information that is generated by the calibration function. These registers contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0], CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically set once the self calibration sequence is done (CAL is cleared).
PAGE 605
Chapter 31 Analog-to-Digital Converter (ADC) 31.3.20 ADC minus-side general calibration value register (ADCx_CLM4) For more information, refer to CLMD register description.
PAGE 606
Register Definition 31.3.22 ADC minus-side general calibration value register (ADCx_CLM2) For more information, refer to CLMD register description.
PAGE 607
Chapter 31 Analog-to-Digital Converter (ADC) 31.3.24 ADC minus-side general calibration value register (ADCx_CLM0) For more information, refer to CLMD register description.
PAGE 608
Functional description The ADC module has the capability of automatically averaging the result of multiple conversions. The hardware average function is enabled by setting the AVGE bit and operates with any of the conversion modes and configurations. NOTE For the chip specific modes of operation, refer to the Power Management information of this MCU. 31.4.1 Clock select and divide control One of four clock sources can be selected as the clock source for the ADC module.
PAGE 609
Chapter 31 Analog-to-Digital Converter (ADC) 31.4.2 Voltage reference selection The ADC can be configured to accept one of the two voltage reference pairs as the reference voltage (VREFSH and VREFSL) used for conversions. Each pair contains a positive reference that must be between the minimum Ref Voltage High and VDDA, and a ground reference that must be at the same potential as VSSA. The two pairs are external (VREFH and VREFL) and alternate (VALTH and VALTL).
PAGE 610
Functional description When the conversion is completed, the result is placed in the data registers associated with the ADHWTSn received (ADHWTSA active selects RA register; ADHWTSn active selects Rn register). The conversion complete flag associated with the ADHWTSn received (the COCO bit in SC1n register) is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled (AIEN=1). 31.4.
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Chapter 31 Analog-to-Digital Converter (ADC) If continuous conversions are enabled, a new conversion is automatically initiated after the completion of the current conversion. In software triggered operation (ADTRG=0), continuous conversions begin after SC1A register is written and continue until aborted. In hardware triggered operation (ADTRG=1 and one ADHWTSn event has occurred), continuous conversions begin after a hardware trigger event and continue until aborted.
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Functional description • The MCU is reset or enters Low Power Stop modes. • The MCU enters Normal Stop mode with ADACK not enabled. When a conversion is aborted, the contents of the data registers, Rn, are not altered. The data registers continue to be the values transferred after the completion of the last successful conversion. If the conversion was aborted by a reset or Low Power Stop modes, RA and R n return to their reset states. 31.4.4.
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Chapter 31 Analog-to-Digital Converter (ADC) ADC Configuration 1 11 Sample time (ADCK cycles) 1 8 The total conversion time depends upon: the sample time (as determined by ADLSMP and ADLSTS bits), the MCU bus frequency, the conversion mode (as determined by MODE and SC1n[DIFF] bits), the high speed configuration (ADHSC bit), and the frequency of the conversion clock (fADCK). The ADHSC bit is used to configure a higher clock input frequency. This will allow faster overall conversion times.
PAGE 614
Functional description Table 31-71. Average number factor (AverageNum) AVGE AVGS[1:0] Average number factor (AverageNum) 0 xx 1 1 00 4 1 01 8 1 10 16 1 11 32 Table 31-72. Base Conversion Time (BCT) Mode Base conversion time (BCT) 8b s.e. 17 ADCK cycles 9b diff 27 ADCK cycles 10b s.e. 20 ADCK cycles 11b diff 30 ADCK cycles 12b s.e. 20 ADCK cycles 13b diff 30 ADCK cycles 16b s.e. 25 ADCK cycles 16b diff 34 ADCK cycles Table 31-73.
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Chapter 31 Analog-to-Digital Converter (ADC) 31.4.4.6 Conversion time examples The following examples use Figure 31-62 and the information provided in Table 31-70 through Table 31-74. 31.4.4.6.1 Typical conversion time configuration A typical configuration for ADC conversion is: 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 MHz, long sample time disabled and high speed conversion disabled.
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Functional description Table 31-76. Typical conversion time (continued) Variable Time HSCAdder 0 The resulting conversion time is generated using the parameters listed in the preceding table. Therefore, for bus clock equal to 8 MHz and ADCK equal to 1 MHz, the resulting conversion time is 57.625 µs (AverageNum). This results in a total conversion time of 1.844 ms. 31.4.4.6.
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Chapter 31 Analog-to-Digital Converter (ADC) After the selected input is sampled and converted, the result is placed in an accumulator from which an average is calculated once the selected number of conversions has been completed. When hardware averaging is selected, the completion of a single conversion will not set the COCO bit.
PAGE 618
Functional description With the ADC range enable bit set, ACREN =1, and if compare value register 1 (CV1 value) is less than or equal to the compare value register 2 (CV2 value), then setting ACFGT will select a trigger-if-inside-compare-range inclusive-of-endpoints function. Clearing ACFGT will select a trigger-if-outside-compare-range, not-inclusive-ofendpoints function. If CV1 is greater than CV2, setting ACFGT will select a trigger-if-outside-comparerange, inclusive-of-endpoints function.
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Chapter 31 Analog-to-Digital Converter (ADC) for the different configurations. For best calibration results, it is recommended to set hardware averaging to maximum (AVGE=1, AVGS=11 for average of 32), ADC clock frequency fADCK less than or equal to 4 MHz, VREFH=VDDA, and to calibrate at nominal voltage and temperature. The input channel, conversion mode continuous function, compare function, resolution mode, and differential/single-ended mode are all ignored during the calibration function.
PAGE 620
Functional description stored in flash memory after an initial calibration and recovered prior to the first ADC conversion. This method should reduce the calibration latency to 20 register store operations on all subsequent power, reset, or Low Power Stop mode recoveries. 31.4.7 User defined offset function The ADC offset correction register (OFS) contains the user selected or calibration generated offset error correction value. This register is a 2’s complement, left justified.
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Chapter 31 Analog-to-Digital Converter (ADC) format and the effect will be an addition. An offset correction that results in an out-ofrange value will be forced to the minimum or maximum value (the minimum value for single-ended conversions is 0x0000; for a differential conversion it is 0x8000). To preserve accuracy, the calibrated offset value initially stored in the OFS register must be added to the user defined offset.
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Functional description 31.4.9 MCU wait mode operation Wait mode is a lower power-consumption standby mode from which recovery is fast because the clock sources remain active. If a conversion is in progress when the MCU enters Wait mode, it continues until completion. Conversions can be initiated while the MCU is in Wait mode by means of the hardware trigger or if continuous conversions are enabled.
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Chapter 31 Analog-to-Digital Converter (ADC) 31.4.10.2 Normal Stop mode with ADACK enabled If ADACK is selected as the conversion clock, the ADC continues operation during Normal Stop mode. Refer to the Chip Configuration chapter for configuration information for this MCU. If a conversion is in progress when the MCU enters Normal Stop mode, it continues until completion.
PAGE 624
Initialization information Note Hexadecimal values are designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 31.5.1 ADC module initialization example This section provides details about the ADC module initialization. 31.5.1.1 Initialization sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is as follows: 1.
PAGE 625
Chapter 31 Analog-to-Digital Converter (ADC) Bit 3:2 bit conversion. Bit 1:0 MODE 10 ADICLK Selects the single-ended 10-bit conversion, differential 1100 Selects the bus clock. SC2 = 0x00 (%00000000) Bit Bit Bit Bit Bit Bit Bit and VREFL). 7 6 5 4 3 2 1:0 ADACT ADTRG ACFE ACFGT ACREN DMAEN REFSEL 0 0 0 0 0 0 00 Flag indicates if a conversion is in progress. Software trigger selected. Compare function disabled. Not used in this example. Compare range disabled. DMA request disabled.
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Application information 31.6 Application information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an ADC. 31.6.1 External pins and routing The following sections discuss the external pins associated with the ADC module and how they should be used for best results. 31.6.1.
PAGE 627
Chapter 31 Analog-to-Digital Converter (ADC) are selected using the REFSEL bits in the SC2 register. The alternate (VALTH and VALTL) voltage reference pair may select additional external pins or internal sources depending on MCU configuration. Refer to the Chip Configuration information on the Voltage References specific to this MCU. In some packages, the external or alternate pairs are connected in the package to VDDA and VSSA, respectively.
PAGE 628
Application information For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be transitioning during conversions. 31.6.2 Sources of error Several sources of error exist for A/D conversions. These are discussed in the following sections. 31.6.2.1 Sampling error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. RAS + RADIN =SC / (FMAX * NUMTAU * CADIN) Figure 31-65.
PAGE 629
Chapter 31 Analog-to-Digital Converter (ADC) 31.6.2.3 Noise-induced errors System noise that occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met: • There is a 0.1 μF low-ESR capacitor from VREFH to VREFL. • There is a 0.1 μF low-ESR capacitor from VDDA to VSSA. • If inductive isolation is used from the primary supply, an additional 1 μF capacitor is placed from VDDA to VSSA.
PAGE 630
Application information 31.6.2.4 Code width and quantization error The ADC quantizes the ideal straight-line transfer function into 65536 steps (in 16-bit mode). Each step ideally has the same height (1 code) and width. The width is defined as the delta between the transition points to one code and the next. The ideal code width for an N bit converter (in this case N can be 16, 12, 10, or 8), defined as 1 LSB, is: LSB Figure 31-66.
PAGE 631
Chapter 31 Analog-to-Digital Converter (ADC) • Integral non-linearity (INL): This error is defined as the highest-value the (absolute value of the) running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes.
PAGE 632
Application information K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 632 Freescale Semiconductor, Inc.
PAGE 633
Chapter 32 Comparator (CMP) 32.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The comparator (CMP) module provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage, known as rail-to-rail operation. The Analog MUX (ANMUX) provides a circuit for selecting an analog input signal from eight channels.
PAGE 634
6-bit DAC key features • Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output • Selectable inversion on comparator output • Capability to produce a wide range of outputs such as: • Sampled • Windowed, which is ideal for certain PWM zero-crossing-detection applications • Digitally filtered: • Filter can be bypassed • Can be clocked via external SAMPLE signal or scaled bus clock • External hysteresis can be used at the same time that the output filter is
PAGE 635
Chapter 32 Comparator (CMP) 32.4 ANMUX key features • Two 8-to-1 channel mux • Operational over the entire supply range 32.5 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 Freescale Semiconductor, Inc.
PAGE 636
CMP block diagram VRSEL Vin1 Vin2 VOSEL[5:0] MUX DAC output MUX 64-level DACEN DAC PSEL[2:0] CMP MUX Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Reference Input 5 Reference Input 6 INP Sample input CMP MUX ANMUX Window and filter control INM IRQ CMPO MSEL[2:0] Figure 32-1. CMP, DAC and ANMUX block diagram 32.6 CMP block diagram The following figure shows the block diagram for the CMP module. K20 Sub-Family Reference Manual, Rev.
PAGE 637
Chapter 32 Comparator (CMP) Internal bus FILT_PER EN,PMODE,HYSCTRL[1:0] COS INV OPE WE FILTER_CNT SE COUT IER/F CFR/F INP + - CMPO Polarity select Window control Interrupt control Filter block INM IRQ COUT To other SOC functions WINDOW/SAMPLE bus clock Clock prescaler FILT_PER 1 0 0 divided bus clock COUTA CGMUX SE 1 CMPO to PAD COS Figure 32-2.
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Memory map/register definitions • If enabled, the Filter block will incur up to one bus clock additional latency penalty on COUT due to the fact that COUT, which is crossing clock domain boundaries, must be resynchronized to the bus clock. • CR1[WE] and CR1[SE] are mutually exclusive. 32.7 Memory map/register definitions CMP memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4007_3000 CMP Control Register 0 (CMP0_CR0) 8 R/W 00h 32.7.
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Chapter 32 Comparator (CMP) 32.7.1 CMP Control Register 0 (CMPx_CR0) Addresses: CMP0_CR0 is 4007_3000h base + 0h offset = 4007_3000h CMP1_CR0 is 4007_3008h base + 0h offset = 4007_3008h Bit 7 Read Write Reset 0 6 5 4 FILTER_CNT 0 0 0 0 3 2 0 0 0 0 1 0 HYSTCTR 0 0 CMPx_CR0 field descriptions Field 7 Reserved 6–4 FILTER_CNT Description This read-only field is reserved and always has the value zero.
PAGE 640
Memory map/register definitions 32.7.2 CMP Control Register 1 (CMPx_CR1) Addresses: CMP0_CR1 is 4007_3000h base + 1h offset = 4007_3001h CMP1_CR1 is 4007_3008h base + 1h offset = 4007_3009h Bit Read Write Reset 7 6 SE WE 0 0 5 0 4 3 2 1 0 PMODE INV COS OPE EN 0 0 0 0 0 0 CMPx_CR1 field descriptions Field 7 SE Description Sample Enable At any given time, either SE or WE can be set. If a write to this register attempts to set both, then SE is set and WE is cleared.
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Chapter 32 Comparator (CMP) CMPx_CR1 field descriptions (continued) Field 1 OPE Description Comparator Output Pin Enable 0 1 0 EN CMPO is not available on the associated CMPO output pin. CMPO is available on the associated CMPO output pin. Comparator Module Enable Enables the Analog Comparator module. When the module is not enabled, it remains in the off state, and consumes no power.
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Memory map/register definitions CMPx_SCR field descriptions Field 7 Reserved 6 DMAEN Description This read-only field is reserved and always has the value zero. DMA Enable Control Enables the DMA transfer triggered from the CMP module. When this field is set, a DMA request is asserted when CFR or CFF is set. 0 1 5 Reserved 4 IER This read-only field is reserved and always has the value zero. Comparator Interrupt Enable Rising Enables the CFR interrupt from the CMP.
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Chapter 32 Comparator (CMP) 32.7.5 DAC Control Register (CMPx_DACCR) Addresses: CMP0_DACCR is 4007_3000h base + 4h offset = 4007_3004h CMP1_DACCR is 4007_3008h base + 4h offset = 4007_300Ch Bit Read Write Reset 7 6 5 DACEN VRSEL 0 0 4 3 2 1 0 0 0 0 VOSEL 0 0 0 CMPx_DACCR field descriptions Field 7 DACEN Description DAC Enable Enables the DAC. When the DAC is disabled, it is powered down to conserve power. 0 1 DAC is disabled. DAC is enabled.
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CMP functional description CMPx_MUXCR field descriptions (continued) Field Description NOTE: When an inappropriate operation selects the same input for both muxes, the comparator automatically shuts down to prevent itself from becoming a noise generator. 000 001 010 011 100 101 110 111 2–0 MSEL IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 Minus Input Mux Control Determines which input is selected for the minus input of the comparator. For INx inputs, see CMP, DAC, and ANMUX block diagrams.
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Chapter 32 Comparator (CMP) • The comparator itself • The window function • The filter function The filter, CR0[FILTER_CNT], can be clocked from an internal or external clock source. The filter is programmable with respect to the number of samples that must agree before a change in the output is registered. In the simplest case, only one sample must agree. In this case, the filter acts as a simple sampler. The external sample input is enabled using CR1[SE].
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CMP functional description Table 32-22. Comparator sample/filter controls (continued) Mode # CR1[EN] CR1[WE] CR1[SE] CR0[FILTER_C NT] FPR[FILT_PER] Operation 6 1 1 0 0x01 0x01–0xFF Windowed/Resampled mode Comparator output is sampled on every rising bus clock edge when SAMPLE=1 to generate COUTA, which is then resampled on an interval determined by FILT_PER to generate COUT. See the Windowed/Resampled mode (# 6).
PAGE 647
Chapter 32 Comparator (CMP) 32.8.1.2 Continuous mode (#s 2A & 2B) Internal bus EN,PMODE,HYSTCTR[1:0] FILT_PER INV COS WE OPE FILTER_CNT SE COUT IER/F CFR/F 0 INP + - CMPO Polarity select Window control Filter block Interrupt control INM IRQ COUT To other SOC functions WINDOW/SAMPLE bus clock FILT_PER Clock prescaler 1 0 0 divided bus clock COUTA CGMUX SE 1 CMPO to PAD COS Figure 32-21.
PAGE 648
CMP functional description 32.8.1.3 Sampled, Non-Filtered mode (#s 3A & 3B) Internal bus EN,PMODE,HYSTCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT 0x01 0 IER/F CFR/F 1 INP + - CMPO Polarity select Window control Filter block Interrupt control INM IRQ COUT To other SOC functions WINDOW/SAMPLE bus clock FILT_PER Clock prescaler 1 0 0 divided bus clock COUTA CGMUX SE=1 1 CMPO to PAD COS Figure 32-22.
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Chapter 32 Comparator (CMP) Internal bus EN,PMODE,HYSTCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT 0 IER/F CFR/F 0 0x01 INP + - CMPO Polarity select Window control Filter block Interrupt control INM IRQ COUT WINDOW/SAMPLE bus clock FILT_PER Clock prescaler To other SOC functions 1 0 0 divided bus clock COUTA CGMUX SE=0 1 CMPO to PAD COS Figure 32-23. Sampled, Non-Filtered (# 3B): sampling interval internally derived 32.8.1.
PAGE 650
CMP functional description Internal bus EN, PMODE, HYSTCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT > 0x01 0 INP + - CMPO Polarity select Window control IER/F CFR/F 1 Interrupt control Filter block INM IRQ COUT To other SOC functions WINDOW/SAMPLE bus clock FILT_PER Clock prescaler 1 0 0 divided bus clock COUTA CGMUX SE=1 1 CMPO to PAD COS Figure 32-24. Sampled, Filtered (# 4A): sampling point externally driven K20 Sub-Family Reference Manual, Rev.
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Chapter 32 Comparator (CMP) Internal bus OPE FILT_PER EN, PMODE,HYSTCTR[1:0] COS INV WE FILTER_CNT SE COUT IER/F CFR/F >0x01 0 1 INP + - Polarity CMPO select Window control Filter block Interrupt control INM IRQ COUT WINDOW/SAMPLE bus clock FILT_PER Clock prescaler To other SOC functions 1 0 0 divided bus clock COUTA CGMUX SE=0 1 CMPO to PAD COS Figure 32-25.
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CMP functional description WI NDOW Plus input Minus input CMPO COUTA Figure 32-26. Windowed mode operation Internal bus EN, PMODE,HYSCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT 0x01 IER/F CFR/F 0 INP + - CMPO Polarity select Window control Interrupt control Filter block INM IRQ COUT To other SOC functions WINDOW/SAMPLE bus clock FILT_PER Clock prescaler 1 0 0 divided bus clock COUTA CGMUX SE=0 1 CMPO to PAD COS Figure 32-27.
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Chapter 32 Comparator (CMP) When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. 32.8.1.6 Windowed/Resampled mode (# 6) The following figure uses the same input stimulus shown in Figure 32-26, and adds resampling of COUTA to generate COUT. Samples are taken at the time points indicated by the arrows in the figure. Again, prop delays and latency are ignored for the sake of clarity.
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CMP functional description 32.8.1.7 Windowed/Filtered mode (#7) This is the most complex mode of operation for the comparator block, as it uses both windowing and filtering features. It also has the highest latency of any of the modes. This can be approximated: up to 1 bus clock synchronization in the window function + ((CR0[FILTER_CNT] * FPR[FILT_PER]) + 1) * bus clock for the filter function. When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1.
PAGE 655
Chapter 32 Comparator (CMP) 32.8.2.2 Stop mode operation Subject to platform-specific clock restrictions, the MCU is brought out of stop when a compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE] is enabled, the comparator output operates as in the normal operating mode and comparator output is placed onto the external pin.
PAGE 656
CMP functional description During operation, the propagation delay of the selected data paths must always be considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF] to reflect an input change or a configuration change to one of the components involved in the data path. When programmed for filtering modes, COUT will initially be equal to 0, until sufficient clock cycles have elapsed to fill all stages of the filter. This occurs even if COUTA is at a logic 1. 32.8.
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Chapter 32 Comparator (CMP) Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates switching current associated with the filtering process. Note Always switch to this setting prior to making any changes in filter parameters. This resets the filter to a known state. Switching CR0[FILTER_CNT] on the fly without this intermediate step can result in unexpected behavior. If CR1[SE]=1, the filter takes samples of COUTA on each positive transition of the sample input.
PAGE 658
CMP interrupts Table 32-23.
PAGE 659
Chapter 32 Comparator (CMP) 32.11 Digital-to-analog converter block diagram The following figure shows the block diagram of the DAC module. It contains a 64-tap resistor ladder network and a 64-to-1 multiplexer, which selects an output voltage from one of 64 distinct levels that outputs from DACO. It is controlled through the DAC Control Register (DACCR). Its supply reference source can be selected from two sources Vin1 and Vin2. The module can be powered down or disabled when not in use.
PAGE 660
DAC resets 32.13 DAC resets This module has a single reset input, corresponding to the chip-wide peripheral reset. 32.14 DAC clocks This module has a single clock input, the bus clock. 32.15 DAC interrupts This module has no interrupts. K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 660 Freescale Semiconductor, Inc.
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Chapter 33 Voltage Reference (VREFV1) 33.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Voltage Reference(VREF) is intended to supply an accurate voltage output that can be trimmed in 0.5 mV steps. The VREF can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC, DAC, or CMP.
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Introduction 6 BITS 1.75 V Regulator TRM SC[VREFEN] SC[MODE_LV] 1.75 V 2 BITS SC[VREFST] BANDGAP VDDA DEDICATED OUTPUT PIN VREF_OUT 100nF REGULATION BUFFER Figure 33-1. Voltage reference block diagram 33.1.1 Overview The Voltage Reference provides a buffered reference voltage for use as an external reference. In addition, the buffered reference is available internally for use with on chip peripherals such as ADCs and DACs. Refer to the chip configuration chapter for a description of these options.
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Chapter 33 Voltage Reference (VREFV1) • Bandgap enabled/standby (output buffer disabled) • Low power buffer mode (output buffer enabled) • High power buffer mode (output buffer enabled) • 1.2 V output at room temperature • Dedicated output pin, VREF_OUT 33.1.3 Modes of Operation The Voltage Reference continues normal operation in Run, Wait, and Stop modes. The Voltage Reference can also run in Very Low Power Run (VLPR), Very Low Power Wait (VLPW) and Very Low Power Stop (VLPS).
PAGE 664
Memory Map and Register Definition 33.2 Memory Map and Register Definition VREF memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_4000 VREF Trim Register (VREF_TRM) 8 R/W See section 33.2.1/ 664 4007_4001 VREF Status and Control Register (VREF_SC) 8 R/W 00h 33.2.2/ 665 33.2.1 VREF Trim Register (VREF_TRM) This register contains bits that contain the trim data for the Voltage Reference.
PAGE 665
Chapter 33 Voltage Reference (VREFV1) VREF_TRM field descriptions (continued) Field Description 000000 .... 111111 Min .... Max 33.2.2 VREF Status and Control Register (VREF_SC) This register contains the control bits used to enable the internal voltage reference and to select the buffer mode to be used.
PAGE 666
Functional Description VREF_SC field descriptions (continued) Field Description 4 Reserved This read-only field is reserved and always has the value zero. 3 Reserved This read-only field is reserved and always has the value zero. 2 VREFST Internal Voltage Reference stable This bit indicates that the bandgap reference within the Voltage Reference module has completed its startup and stabilization. 0 1 1–0 MODE_LV The module is disabled or not stable. The module is stable.
PAGE 667
Chapter 33 Voltage Reference (VREFV1) 33.3.1 Voltage Reference Disabled, SC[VREFEN] = 0 When SC[VREFEN] = 0, the Voltage Reference is disabled, the VREF bandgap and the output buffers are disabled. The Voltage Reference is in off mode. 33.3.2 Voltage Reference Enabled, SC[VREFEN] = 1 When SC[VREFEN] = 1, the Voltage Reference is enabled, and different modes should be set by the SC[MODE_LV] bits. 33.3.2.1 SC[MODE_LV]=00 The internal VREF bandgap is enabled to generate an accurate 1.
PAGE 668
Initialization/Application Information 33.3.2.3 SC[MODE_LV] = 10 The internal VREF bandgap is on. The low power buffer is enabled to generate a buffered 1.2 V voltage to VREF_OUT. It can also be used as a reference to internal analog peripherals such as an ADC channel or analog comparator input. If this mode is entered from the standby mode (SC[MODE_LV] = 00, SC[VREFEN] = 1) there will be a delay before the buffer output is settled at the final value.
PAGE 669
Chapter 34 Programmable Delay Block (PDB) 34.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The programmable delay block (PDB) provides controllable delays from either an internal or an external trigger, or a programmable interval tick, to the hardware trigger inputs of ADCs and/or generates the interval triggers to DACs, so that the precise timing between ADC conversions and/or DAC updates can be achieved.
PAGE 670
Introduction • Optional back-to-back mode operation, which enables the ADC conversions complete to trigger the next PDB channel • One programmable delay interrupt • One sequence error interrupt • One channel flag and one sequence error flag per pre-trigger • DMA support • Up to eight pulse outputs (pulse-out's) • Pulse-out's can be enabled or disabled independently. • Programmable pulse width NOTE The number of PDB input and output triggers are chip-specific.
PAGE 671
Chapter 34 Programmable Delay Block (PDB) 34.1.3 Back-to-back Acknowledgement Connections PDB back-to-back operation acknowledgment connections are chip-specific. For implementation, refer to the Chip Configuration information. 34.1.4 Block Diagram This diagram illustrates the major components of the PDB. K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 Freescale Semiconductor, Inc.
PAGE 672
Introduction Ack 0 PDBCHnDLY0 = Pre-trigger 0 BB[0], TOS[0] Ch n pre-trigger 0 EN[0] Ack m PDBCHnDLYm = Pre-trigger m BB[m], TOS[m] Ch n pre-trigger m EN[m] Sequence Error Detection ERR[M - 1:0] Ch n trigger PDBMOD PDBCNT = PDB Counter Control Logic DACINTx CONT DAC interval trigger x = DAC Interval Counter x TOEx MULT EXTx DAC ext trigger input x PRESCALER DAC interval trigger x Trigger-In 0 Trigger-In 1 POyDLY1 Trigger-In 14 = SWTRIG POyDLY2 TRIGSEL Pulse Generation = P
PAGE 673
Chapter 34 Programmable Delay Block (PDB) 34.1.5 Modes of Operation PDB ADC trigger operates in the following modes. Disabled: Counter is off, all pre-trigger and trigger outputs are low if PDB is not in backto-back operation of Bypass mode. Debug: Counter is paused when processor is in debug mode, the counter for dac trigger also paused in Debug mode.
PAGE 674
Memory Map and Register Definition PDB memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4003_6000 Status and Control Register (PDB0_SC) 32 R/W 0000_0000h 34.3.1/ 674 4003_6004 Modulus Register (PDB0_MOD) 32 R/W 0000_FFFFh 34.3.2/ 677 4003_6008 Counter Register (PDB0_CNT) 32 R 0000_0000h 34.3.3/ 677 4003_600C Interrupt Delay Register (PDB0_IDLY) 32 R/W 0000_FFFFh 34.3.
PAGE 675
Chapter 34 Programmable Delay Block (PDB) PDBx_SC field descriptions Field 31–20 Reserved 19–18 LDMOD Description This read-only field is reserved and always has the value zero. Load Mode Select Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers, after 1 is written to LDOK. 00 01 10 11 17 PDBEIE The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.
PAGE 676
Memory Map and Register Definition PDBx_SC field descriptions (continued) Field Description Selects the trigger input source for the PDB. The trigger input source can be internal or external (EXTRG pin), or the software trigger. Please refer to Chip Configuration chapter for the actual PDB input trigger connections.
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Chapter 34 Programmable Delay Block (PDB) PDBx_SC field descriptions (continued) Field Description 0 1 0 LDOK PDB operation in One-Shot mode PDB operation in Continuous mode Load OK Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm, DACINTx, and POyDLY with the values written to their buffers. The MOD, IDLY, CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD.
PAGE 678
Memory Map and Register Definition PDBx_CNT field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. 15–0 CNT PDB Counter These read-only bits contain the current value of the counter. 34.3.
PAGE 679
Chapter 34 Programmable Delay Block (PDB) PDBx_CHnC1 field descriptions (continued) Field Description 23–16 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable These bits enable the PDB ADC pre-trigger operation as back-to-back mode. Only lower M pre-trigger bits are implemented in this MCU.
PAGE 680
Memory Map and Register Definition PDBx_CHnS field descriptions (continued) Field Description 7–0 ERR PDB Channel Sequence Error Flags Only the lower M bits are implemented in this MCU. 0 1 Sequence error not detected on PDB channel's corresponding pre-trigger. Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n.
PAGE 681
Chapter 34 Programmable Delay Block (PDB) PDBx_CHnDLY1 field descriptions (continued) Field Description 15–0 DLY PDB Channel Delay These bits specify the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these bits returns the value of internal register that is effective for the current PDB cycle. 34.3.
PAGE 682
Functional Description PDBx_POnDLY field descriptions (continued) Field 15–0 DLY2 Description PDB Pulse-Out Delay 2 These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes low when the PDB counter is equal to the DLY2. Reading these bits returns the value of internal register that is effective for the current PDB cycle. 34.4 Functional Description 34.4.1 PDB Pre-trigger and Trigger Outputs The PDB contains a counter whose output is compared against several different digital values.
PAGE 683
Chapter 34 Programmable Delay Block (PDB) Trigger input event Ch n pre-trigger 0 Ch n pre-trigger 1 ... ... ... ... Ch n pre-trigger M Ch n trigger Figure 34-34. Pre-trigger and Trigger Outputs The delay in CHnDLYm register can be optionally bypassed, if CHnC1[TOS[m]] is cleared. In this case, when the trigger input event occurs, the pre-trigger m is asserted after two peripheral clock cycles. The PDB can be configured in back-to-back (B2B) operation.
PAGE 684
Functional Description 34.4.2 PDB Trigger Input Source Selection The PDB has up to 15 trigger input sources, namely Trigger-In 0 to 14. They are connected to on-chip or off-chip event sources. The PDB can be triggered by software through the SC[SWTRIG]. SC[TRIGSEL] bits select the active trigger input source or software trigger. For the trigger input sources implemented in this MCU, refer to Chip Configuration information. 34.4.3 Pulse-Out's PDB can generate pulse outputs of configurable width.
PAGE 685
Chapter 34 Programmable Delay Block (PDB) Table 34-36. Circumstances of Update to the Delay Registers SC[LDMOD] Update to the Delay Registers 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to SC[LDOK]. 01 The PDB counter reaches the MOD register value after 1 is written to SC[LDOK]. 10 A trigger input event is detected after 1 is written to SC[LDOK].
PAGE 686
Application Information 34.4.5 Interrupts PDB can generate two interrupts, PDB interrupt and PDB sequence error interrupt. The following table summarizes the interrupts. Table 34-37. PDB Interrupt Summary Interrupt Flags Enable Bit PDB Interrupt SC[PDBIF] SC[PDBIE] = 1 and SC[DMAEN] = 0 PDB Sequence Error Interrupt CHnS[ERRm] SC[PDBEIE] = 1 34.4.6 DMA If SC[DMAEN] is set, PDB can generate DMA transfer request when SC[PDBIF] is set. When DMA is enabled, the PDB interrupt will not be issued. 34.
PAGE 687
Chapter 35 FlexTimer Module (FTM) 35.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The FlexTimer module (FTM) is a two-to-eight channel timer that supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. The FTM time reference is a 16-bit counter that can be used as an unsigned or signed counter. 35.1.
PAGE 688
Introduction Motor control and power conversion features have been added through a dedicated set of registers and defaults turn off all new features. The new features, such as hardware deadtime insertion, polarity, fault control, and output forcing and masking, greatly reduce loading on the execution software and are usually each controlled by a group of registers. FlexTimer input triggers can be from comparators, ADC, or other submodules to initiate timer functions automatically.
PAGE 689
Chapter 35 FlexTimer Module (FTM) • The capture can occur on rising edges, falling edges or both edges • An input filter can be selected for some channels • In Output Compare mode the output signal can be set, cleared, or toggled on match • All channels can be configured for center-aligned PWM mode • Each pair of channels can be combined to generate a PWM signal with independent control of both edges of PWM signal • The FTM channels can operate as pairs with equal outputs, pairs with complementary outputs,
PAGE 690
Introduction real time reference or provide the interrupt sources needed to wake the MCU from Wait mode, the power can then be saved by disabling FTM functions before entering Wait mode. 35.1.4 Block diagram The FTM uses one input/output (I/O) pin per channel, CHn (FTM channel (n)) where n is the channel number (0–7). The following figure shows the FTM structure. The central component of the FTM is the 16-bit counter with programmable initial and final values and its counting can be up or up-down.
PAGE 691
Chapter 35 FlexTimer Module (FTM) CLKS FTMEN QUADEN no clock selected (FTM counter disable) system clock fixed frequency clock external clock phase A phase B PS prescaler (1, 2, 4, 8, 16, 32, 64 or 128) synchronizer Quadrature decoder QUADEN CPWMS CAPTEST INITTRIGEN CNTIN FAULTM[1:0] FFVAL[3:0] FAULTIE FAULTnEN* FFLTRnEN* FTM counter FAULTIN FAULTF FAULTFn* fault control fault input n* CH0IE CH0F input capture mode logic C0V input capture mode logic C1V DECAPEN COMBINE0 CPWMS MS1B:MS1A ELS1B
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FTM signal descriptions 35.2 FTM signal descriptions Table 35-1 shows the user-accessible signals for the FTM. Table 35-1. FTM signal descriptions Signal EXTCLK CHn Description External clock. FTM external clock can be selected to drive the FTM counter. FTM channel (n), where n can be 7-0 I/O Function I The external clock input signal is used as the FTM counter clock if selected by CLKS[1:0] bits in the SC register. This clock signal must not exceed 1/4 of system clock frequency.
PAGE 693
Chapter 35 FlexTimer Module (FTM) The second set has the FTM specific registers. Any second set registers, or bits within these registers, that are used by an unavailable function in the FTM configuration remain in the memory map and in the reset value, so they have no active function. Note Do not write to the FTM specific registers (second set registers) when FTMEN = 0. 35.3.2 Register descriptions Accesses to reserved addresses result in transfer errors.
PAGE 694
Memory map and register definition FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_8030 Channel (n) Value (FTM0_C4V) 32 R/W 0000_0000h 35.3.7/ 703 4003_8034 Channel (n) Status And Control (FTM0_C5SC) 32 R/W 0000_0000h 35.3.6/ 700 4003_8038 Channel (n) Value (FTM0_C5V) 32 R/W 0000_0000h 35.3.7/ 703 4003_803C Channel (n) Status And Control (FTM0_C6SC) 32 R/W 0000_0000h 35.3.
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Chapter 35 FlexTimer Module (FTM) FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_8080 Quadrature Decoder Control And Status (FTM0_QDCTRL) 32 R/W 0000_0000h 35.3.21/ 729 4003_8084 Configuration (FTM0_CONF) 32 R/W 0000_0000h 35.3.22/ 731 4003_8088 FTM Fault Input Polarity (FTM0_FLTPOL) 32 R/W 0000_0000h 35.3.23/ 733 4003_808C Synchronization Configuration (FTM0_SYNCONF) 32 R/W 0000_0000h 35.3.
PAGE 696
Memory map and register definition FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_9034 Channel (n) Status And Control (FTM1_C5SC) 32 R/W 0000_0000h 35.3.6/ 700 4003_9038 Channel (n) Value (FTM1_C5V) 32 R/W 0000_0000h 35.3.7/ 703 4003_903C Channel (n) Status And Control (FTM1_C6SC) 32 R/W 0000_0000h 35.3.6/ 700 4003_9040 Channel (n) Value (FTM1_C6V) 32 R/W 0000_0000h 35.3.
PAGE 697
Chapter 35 FlexTimer Module (FTM) FTM memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4003_9084 Configuration (FTM1_CONF) 32 R/W 0000_0000h 35.3.22/ 731 4003_9088 FTM Fault Input Polarity (FTM1_FLTPOL) 32 R/W 0000_0000h 35.3.23/ 733 4003_908C Synchronization Configuration (FTM1_SYNCONF) 32 R/W 0000_0000h 35.3.24/ 734 4003_9090 FTM Inverting Control (FTM1_INVCTRL) 32 R/W 0000_0000h 35.3.
PAGE 698
Memory map and register definition FTMx_SC field descriptions (continued) Field Description If another FTM overflow occurs between the read and write operations, the write operation has no effect; therefore, TOF remains set indicating an overflow has occurred. In this case, a TOF interrupt request is not lost due to the clearing sequence for a previous TOF. 0 1 6 TOIE Timer Overflow Interrupt Enable Enables FTM overflow interrupts. 0 1 5 CPWMS FTM counter has not overflowed.
PAGE 699
Chapter 35 FlexTimer Module (FTM) Reset clears the CNT register. Writing any value to COUNT updates the counter with its initial value, CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you may read.
PAGE 700
Memory map and register definition FTMx_MOD field descriptions Field 31–16 Reserved 15–0 MOD Description This field is reserved. Modulo Value 35.3.6 Channel (n) Status And Control (FTMx_CSC) CnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. Table 35-67.
PAGE 701
Chapter 35 FlexTimer Module (FTM) Table 35-67. Mode, edge, and level selection (continued) DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration 0 0 0 0 1 Input Capture Capture on Rising Edge Only 1 1X 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge 1 Output Compare 10 Clear Output on match 11 Set Output on match 10 Edge-Aligned PWM X1 1 XX 10 0 XX 10 Center-Aligned PWM 0 0 X0 X1 See the following table (Table 35-8).
PAGE 702
Memory map and register definition Table 35-68.
PAGE 703
Chapter 35 FlexTimer Module (FTM) FTMx_CnSC field descriptions (continued) Field Description Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See Table 35-7. This field is write protected. It can be written only when MODE[WPDIS] = 1. 3 ELSB Edge or Level Select The functionality of ELSB and ELSA depends on the channel mode. See Table 35-7. This field is write protected. It can be written only when MODE[WPDIS] = 1.
PAGE 704
Memory map and register definition FTMx_CnV field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. 15–0 VAL Channel Value Captured FTM counter value of the input modes or the match value for the output modes 35.3.8 Counter Initial Value (FTMx_CNTIN) The Counter Initial Value register contains the initial value for the FTM counter. Writing to the CNTIN register latches the value into a buffer.
PAGE 705
Chapter 35 FlexTimer Module (FTM) Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be checked using only one read of STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to STATUS. Hardware sets the individual channel flags when an event occurs on the channel. CHF is cleared by reading STATUS while CHnF is set and then writing a 0 to the CHF bit. Writing a 1 to CHF has no effect.
PAGE 706
Memory map and register definition FTMx_STATUS field descriptions (continued) Field 4 CH4F Description Channel 4 Flag See the register description. 0 1 3 CH3F Channel 3 Flag See the register description. 0 1 2 CH2F See the register description. No channel event has occurred. A channel event has occurred. Channel 1 Flag See the register description. 0 1 0 CH0F No channel event has occurred. A channel event has occurred. Channel 2 Flag 0 1 1 CH1F No channel event has occurred.
PAGE 707
Chapter 35 FlexTimer Module (FTM) Addresses: FTM0_MODE is 4003_8000h base + 54h offset = 4003_8054h FTM1_MODE is 4003_9000h base + 54h offset = 4003_9054h Bit 31 30 29 28 27 26 25 24 0 0 0 0 19 18 17 16 0 0 0 0 11 10 9 8 0 R W Reset 0 0 0 0 Bit 23 22 21 20 0 R W Reset 0 0 0 0 Bit 15 14 13 12 0 R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CAPTEST PWMSYNC WPDIS INIT FTMEN 0 0 1 0 0 R W Reset FAULTIE 0 FAULTM 0 0 FTMx_MODE fie
PAGE 708
Memory map and register definition FTMx_MODE field descriptions (continued) Field 3 PWMSYNC Description PWM Synchronization Mode Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. See PWM synchronization. The PWMSYNC bit configures the synchronization when SYNCMODE is zero. 0 1 2 WPDIS Write Protection Disable When write protection is enabled (WPDIS = 0), write protected bits cannot be written.
PAGE 709
Chapter 35 FlexTimer Module (FTM) The selection of the loading point, CNTMAX and CNTMIN bits, is intended to provide the update of MOD, CNTIN, and CnV registers across all enabled channels simultaneously. The use of the loading point selection together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2 bits, is likely to result in unpredictable behavior. The synchronization event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF register) bits.
PAGE 710
Memory map and register definition FTMx_SYNC field descriptions (continued) Field Description 0 1 5 TRIG1 PWM Synchronization Hardware Trigger 1 Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1 happens when a rising edge is detected at the trigger 1 input signal. 0 1 4 TRIG0 Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0 happens when a rising edge is detected at the trigger 0 input signal.
PAGE 711
Chapter 35 FlexTimer Module (FTM) 35.3.
PAGE 712
Memory map and register definition FTMx_OUTINIT field descriptions (continued) Field Description 0 1 1 CH1OI The initialization value is 0. The initialization value is 1. Channel 1 Output Initialization Value Selects the value that is forced into the channel output when the initialization occurs. 0 1 0 CH0OI The initialization value is 0. The initialization value is 1. Channel 0 Output Initialization Value Selects the value that is forced into the channel output when the initialization occurs.
PAGE 713
Chapter 35 FlexTimer Module (FTM) FTMx_OUTMASK field descriptions (continued) Field 6 CH6OM Description Channel 6 Output Mask Defines if the channel output is masked or unmasked. 0 1 5 CH5OM Channel 5 Output Mask Defines if the channel output is masked or unmasked. 0 1 4 CH4OM Defines if the channel output is masked or unmasked. Defines if the channel output is masked or unmasked. Defines if the channel output is masked or unmasked. Channel output is not masked. It continues to operate normally.
PAGE 714
Memory map and register definition 35.3.14 Function For Linked Channels (FTMx_COMBINE) This register contains the control bits used to configure the fault control, synchronization, deadtime insertion, Dual Edge Capture mode, Complementary, and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2, 4, and 6.
PAGE 715
Chapter 35 FlexTimer Module (FTM) FTMx_COMBINE field descriptions (continued) Field 27 DECAP3 Description Dual Edge Capture Mode Captures For n = 6 Enables the capture of the FTM counter value according to the channel (n) input event and the configuration of the dual edge capture bits. This field applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and when the capture of channel (n+1) event is made.
PAGE 716
Memory map and register definition FTMx_COMBINE field descriptions (continued) Field Description 0 1 20 DTEN2 The PWM synchronization in this pair of channels is disabled. The PWM synchronization in this pair of channels is enabled. Deadtime Enable For n = 4 Enables the deadtime insertion in the channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 19 DECAP2 The deadtime insertion in this pair of channels is disabled.
PAGE 717
Chapter 35 FlexTimer Module (FTM) FTMx_COMBINE field descriptions (continued) Field Description This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 13 SYNCEN1 Synchronization Enable For n = 2 Enables PWM synchronization of registers C(n)V and C(n+1)V. 0 1 12 DTEN1 The fault control in this pair of channels is disabled. The fault control in this pair of channels is enabled. The PWM synchronization in this pair of channels is disabled.
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Memory map and register definition FTMx_COMBINE field descriptions (continued) Field Description 0 1 7 Reserved 6 FAULTEN0 Channels (n) and (n+1) are independent. Channels (n) and (n+1) are combined. This read-only field is reserved and always has the value zero. Fault Control Enable For n = 0 Enables the fault control in channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1.
PAGE 719
Chapter 35 FlexTimer Module (FTM) FTMx_COMBINE field descriptions (continued) Field Description 0 1 0 COMBINE0 The channel (n+1) output is the same as the channel (n) output. The channel (n+1) output is the complement of the channel (n) output. Combine Channels For n = 0 Enables the combine feature for channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 Channels (n) and (n+1) are independent. Channels (n) and (n+1) are combined. 35.3.
PAGE 720
Memory map and register definition FTMx_DEADTIME field descriptions (continued) Field Description When DTVAL is 2, 2 counts are inserted. This pattern continues up to a possible 63 counts. This field is write protected. It can be written only when MODE[WPDIS] = 1. 35.3.
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Chapter 35 FlexTimer Module (FTM) FTMx_EXTTRIG field descriptions (continued) Field Description Set by hardware when a channel trigger is generated. Clear TRIGF by reading EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF has no effect. If another channel trigger is generated before the clearing sequence is completed, the sequence is reset so TRIGF remains set after the clear sequence is completed for the earlier TRIGF.
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Memory map and register definition 35.3.17 Channels Polarity (FTMx_POL) This register defines the output polarity of the FTM channels. NOTE The safe value that is driven in a channel output when the fault control is enabled and a fault condition is detected is the inactive state of the channel. That is, the safe value of a channel is the value of its POL bit.
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Chapter 35 FlexTimer Module (FTM) FTMx_POL field descriptions (continued) Field Description This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 3 POL3 The channel polarity is active high. The channel polarity is active low. Channel 3 Polarity Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 2 POL2 The channel polarity is active high. The channel polarity is active low.
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Memory map and register definition 35.3.18 Fault Mode Status (FTMx_FMS) This register contains the fault detection flags, write protection enable bit, and the logic OR of the enabled fault inputs.
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Chapter 35 FlexTimer Module (FTM) FTMx_FMS field descriptions (continued) Field Description 0 1 5 FAULTIN Write protection is disabled. Write protected bits can be written. Write protection is enabled. Write protected bits cannot be written. Fault Inputs Represents the logic OR of the enabled fault inputs after their filter (if their filter is enabled) when fault control is enabled. 0 1 The logic OR of the enabled fault inputs is 0. The logic OR of the enabled fault inputs is 1.
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Memory map and register definition FTMx_FMS field descriptions (continued) Field Description 0 FAULTF0 Fault Detection Flag 0 Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault condition is detected at the fault input. Clear FAULTF0 by reading the FMS register while FAULTF0 is set and then writing a 0 to FAULTF0 while there is no existing fault condition at the the corresponding fault input. Writing a 1 to FAULTF0 has no effect.
PAGE 727
Chapter 35 FlexTimer Module (FTM) FTMx_FILTER field descriptions (continued) Field 7–4 CH1FVAL Description Channel 1 Input Filter Selects the filter value for the channel input. The filter is disabled when the value is zero. 3–0 CH0FVAL Channel 0 Input Filter Selects the filter value for the channel input. The filter is disabled when the value is zero. 35.3.20 Fault Control (FTMx_FLTCTRL) This register selects the filter value for the fault inputs, enables the fault inputs and the fault inputs filter.
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Memory map and register definition FTMx_FLTCTRL field descriptions (continued) Field Description Selects the filter value for the fault inputs. The fault filter is disabled when the value is zero. NOTE: Writing to this field has immediate effect and must be done only when the fault control or all fault inputs are disabled. Failure to do this could result in a missing fault detection. 7 FFLTR3EN Fault Input 3 Filter Enable Enables the filter for the fault input. This field is write protected.
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Chapter 35 FlexTimer Module (FTM) FTMx_FLTCTRL field descriptions (continued) Field Description This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 0 FAULT0EN Fault input is disabled. Fault input is enabled. Fault Input 0 Enable Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 Fault input is disabled. Fault input is enabled. 35.3.
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Memory map and register definition FTMx_QDCTRL field descriptions (continued) Field Description Enables the filter for the quadrature decoder phase A input. The filter value for the phase A input is defined by the CH0FVAL field of FILTER. The phase A filter is also disabled when CH0FVAL is zero. 0 1 6 PHBFLTREN Phase B Input Filter Enable Enables the filter for the quadrature decoder phase B input. The filter value for the phase B input is defined by the CH1FVAL field of FILTER.
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Chapter 35 FlexTimer Module (FTM) FTMx_QDCTRL field descriptions (continued) Field Description Enables the Quadrature Decoder mode. In this mode, the phase A and B input signals control the FTM counter direction. The Quadrature Decoder mode has precedence over the other modes. See Table 35-7. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 Quadrature Decoder mode is disabled. Quadrature Decoder mode is enabled. 35.3.
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Memory map and register definition FTMx_CONF field descriptions (continued) Field Description 0 1 9 GTBEEN 7–6 BDMMODE A global time base signal generation is enabled. Global Time Base Enable Configures the FTM to use an external global time base signal that is generated by another FTM. 0 1 8 Reserved A global time base signal generation is disabled. Use of an external global time base is disabled. Use of an external global time base is enabled.
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Chapter 35 FlexTimer Module (FTM) 35.3.23 FTM Fault Input Polarity (FTMx_FLTPOL) This register defines the fault inputs polarity.
PAGE 734
Memory map and register definition FTMx_FLTPOL field descriptions (continued) Field Description 0 1 0 FLT0POL The fault input polarity is active high. A one at the fault input indicates a fault. The fault input polarity is active low. A zero at the fault input indicates a fault. Fault Input 0 Polarity Defines the polarity of the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 The fault input polarity is active high.
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Chapter 35 FlexTimer Module (FTM) FTMx_SYNCONF field descriptions Field Description 31–21 Reserved This read-only field is reserved and always has the value zero. 20 HWSOC Software output control synchronization is activated by a hardware trigger. 19 HWINVC Inverting control synchronization is activated by a hardware trigger. 18 HWOM 0 1 0 1 A hardware trigger does not activate the SWOCTRL register synchronization. A hardware trigger activates the SWOCTRL register synchronization.
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Memory map and register definition FTMx_SYNCONF field descriptions (continued) Field Description 0 1 6 Reserved Legacy PWM synchronization is selected. Enhanced PWM synchronization is selected. This read-only field is reserved and always has the value zero. 5 SWOC SWOCTRL Register Synchronization 0 1 4 INVC SWOCTRL register is updated with its buffer value at all rising edges of system clock. SWOCTRL register is updated with its buffer value by the PWM synchronization.
PAGE 737
Chapter 35 FlexTimer Module (FTM) FTMx_INVCTRL field descriptions Field 31–4 Reserved Description This read-only field is reserved and always has the value zero. 3 INV3EN Pair Channels 3 Inverting Enable 2 INV2EN Pair Channels 2 Inverting Enable 1 INV1EN Pair Channels 1 Inverting Enable 0 INV0EN Pair Channels 0 Inverting Enable 0 1 0 1 0 1 0 1 Inverting is disabled. Inverting is enabled. Inverting is disabled. Inverting is enabled. Inverting is disabled. Inverting is enabled.
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Memory map and register definition Addresses: FTM0_SWOCTRL is 4003_8000h base + 94h offset = 4003_8094h FTM1_SWOCTRL is 4003_9000h base + 94h offset = 4003_9094h Bit 31 30 29 28 27 26 25 24 0 0 0 0 19 18 17 16 0 R W Reset 0 0 0 0 Bit 23 22 21 20 0 R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CH7OCV CH6OCV CH5OCV CH4OCV CH3OCV CH2OCV CH1OCV CH0OCV Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CH7OC CH6OC CH5OC CH4OC CH3OC CH2O
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Chapter 35 FlexTimer Module (FTM) FTMx_SWOCTRL field descriptions (continued) Field Description 9 CH1OCV Channel 1 Software Output Control Value 8 CH0OCV Channel 0 Software Output Control Value 7 CH7OC Channel 7 Software Output Control Enable 6 CH6OC Channel 6 Software Output Control Enable 5 CH5OC Channel 5 Software Output Control Enable 4 CH4OC Channel 4 Software Output Control Enable 3 CH3OC Channel 3 Software Output Control Enable 2 CH2OC Channel 2 Software Output Control Enable 1 CH1
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Memory map and register definition 35.3.27 FTM PWM Load (FTMx_PWMLOAD) Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the values of their write buffers when the FTM counter changes from the MOD register value to its next value or when a channel (j) match occurs. A match occurs for the channel (j) when FTM counter = C(j)V.
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Chapter 35 FlexTimer Module (FTM) FTMx_PWMLOAD field descriptions (continued) Field Description 0 1 Do not include the channel in the matching process. Include the channel in the matching process. 5 CH5SEL Channel 5 Select 4 CH4SEL Channel 4 Select 3 CH3SEL Channel 3 Select 2 CH2SEL Channel 2 Select 1 CH1SEL Channel 1 Select 0 CH0SEL Channel 0 Select 0 1 0 1 0 1 0 1 0 1 0 1 Do not include the channel in the matching process. Include the channel in the matching process.
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Functional description FTM counting is up. Channel (n) is in high-true EPWM mode. PS[2:0] = 001 CNTIN = 0x0000 MOD = 0x0004 CnV = 0x0002 prescaler counter FTM counter 1 0 3 1 0 4 1 0 1 0 0 1 1 0 1 0 2 3 1 0 4 1 0 0 1 0 1 0 0 1 2 1 3 1 0 0 4 1 0 1 0 1 1 0 2 channel (n) output counter overflow channel (n) match counter overflow channel (n) match counter overflow channel (n) match Figure 35-125. Notation used 35.4.
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Chapter 35 FlexTimer Module (FTM) The external clock passes through a synchronizer clocked by the system clock to assure that counter transitions are properly aligned to system clock transitions.Therefore, to meet Nyquist criteria considering also jitter, the frequency of the external clock source must not exceed 1/4 of the system clock frequency. 35.4.2 Prescaler The selected counter clock source passes through a prescaler that is a 7-bit counter.
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Functional description The FTM period when using up counting is (MOD – CNTIN + 0x0001) × period of the FTM counter clock. The TOF bit is set when the FTM counter changes from MOD to CNTIN. FTM counting is up.
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Chapter 35 FlexTimer Module (FTM) FTM counting is up CNTIN = 0x0000 MOD = 0x0004 FTM counter 3 4 0 1 2 3 4 0 1 2 3 0 4 1 2 TOF bit set TOF bit set TOF bit set TOF bit period of FTM counter clock period of counting = (MOD - CNTIN + 0x0001) x period of FTM counter clock = (MOD + 0x0001) x period of FTM counter clock Figure 35-128.
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Functional description FTM counting is up MOD = 0x0005 CNTIN = 0x0015 load of CNTIN FTM counter load of CNTIN 0x0005 0x0015 0x0016 ... 0xFFFE 0xFFFF 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0015 0x0016 ... TOF bit set TOF bit set TOF bit Figure 35-129. Example of up counting when the value of CNTIN is greater than the value of MOD 35.4.3.2 Up-down counting Up-down counting is selected when (QUADEN= 0) and (CPWMS = 1).
PAGE 747
Chapter 35 FlexTimer Module (FTM) FTM counting is up-down CNTIN = 0x0000 MOD = 0x0004 FTM counter 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0 1 2 3 4 TOF bit set TOF bit period of FTM counter clock set TOF bit period of counting = 2 x (MOD - CNTIN) x period of FTM counter clock = 2 x MOD x period of FTM counter clock Figure 35-130. Example of up-down counting when CNTIN = 0x0000 Note It is expected that the up-down counting be used only with CNTIN = 0x0000. 35.4.3.
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Functional description 35.4.3.4 Counter reset Any write to CNT resets the FTM counter to the value in the CNTIN register and the channels output to its initial value, except for channels in Output Compare mode. The FTM counter synchronization can also be used to force the value of CNTIN into the FTM counter and the channels output to its initial value, except for channels in Output Compare mode. 35.4.3.
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Chapter 35 FlexTimer Module (FTM) • • • • • DECAPEN = 0 COMBINE = 0 CPWMS = 0 MSnB:MSnA = 0:0 ELSnB:ELSnA ≠ 0:0 When a selected edge occurs on the channel input, the current value of the FTM counter is captured into the CnV register, at the same time the CHnF bit is set and the channel interrupt is generated if enabled by CHnIE = 1. See the following figure. When a channel is configured for input capture, the FTMxCHn pin is an edge-sensitive input.
PAGE 750
Functional description Note The Input Capture mode must be used only with CNTIN = 0x0000. 35.4.4.1 Filter for Input Capture mode The filter function is only available on channels 0, 1, 2, and 3. First, the input signal is synchronized by the system clock. Following synchronization, the input signal enters the filter block. See the following figure.
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Chapter 35 FlexTimer Module (FTM) system clock divided by 4 channel (n) input after the synchronizer 5-bit counter CHnFVAL[3:0] = 0010 (binary value) Time filter output Figure 35-136. Channel input filter example 35.4.5 Output Compare mode The Output Compare mode is selected when: • • • • DECAPEN = 0 COMBINE = 0 CPWMS = 0, and MSnB:MSnA = 0:1 In Output Compare mode, the FTM can generate timed pulses with programmable position, polarity, duration, and frequency.
PAGE 752
Functional description MOD = 0x0005 CnV = 0x0003 CNT channel (n) output CHnF bit ... 0 counter overflow channel (n) match counter overflow 2 1 4 3 5 0 counter overflow channel (n) match 1 2 3 4 5 0 1 ... previous value previous value TOF bit Figure 35-138. Example of the Output Compare mode when the match clears the channel output MOD = 0x0005 CnV = 0x0003 channel (n) match counter overflow CNT channel (n) output CHnF bit ...
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Chapter 35 FlexTimer Module (FTM) The EPWM period is determined by (MOD − CNTIN + 0x0001) and the pulse width (duty cycle) is determined by (CnV − CNTIN). The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel (n) match (FTM counter = CnV), that is, at the end of the pulse width. This type of PWM signal is called edge-aligned because the leading edges of all PWM signals are aligned with the beginning of the period, which is the same for all channels within an FTM.
PAGE 754
Functional description MOD = 0x0008 CnV = 0x0005 counter overflow CNT ... 0 channel (n) match 1 2 3 4 5 counter overflow 6 7 8 0 1 2 ... channel (n) output CHnF bit previous value TOF bit Figure 35-142. EPWM signal with ELSnB:ELSnA = X:1 If (CnV = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal and CHnF bit is not set even when there is the channel (n) match.
PAGE 755
Chapter 35 FlexTimer Module (FTM) The other channel modes are not compatible with the up-down counter (CPWMS = 1). Therefore, all FTM channels must be used in CPWM mode when (CPWMS = 1). FTM counter = CNTIN counter overflow FTM counter = MOD counter overflow FTM counter = MOD channel (n) match (FTM counting is up) channel (n) match (FTM counting is down) channel (n) output pulse width 2 x (CnV - CNTIN) period 2 x (MOD - CNTINCNTIN) Figure 35-143.
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Functional description counter overflow counter overflow MOD = 0x0008 CnV = 0x0005 channel (n) match in down counting CNT ... 7 8 7 6 5 4 3 channel (n) match in up counting 2 1 0 1 2 3 4 5 6 channel (n) match in down counting 7 8 7 6 5 ... channel (n) output CHnF bit previous value TOF bit Figure 35-145.
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Chapter 35 FlexTimer Module (FTM) The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (FTM counter = C(n)V). The CH(n+1)F bit is set and the channel (n +1) interrupt is generated, if CH(n+1)IE = 1, at the channel (n+1) match (FTM counter = C(n+1)V). If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced low at the beginning of the period (FTM counter = CNTIN) and at the channel (n+1) match (FTM counter = C(n +1)V).
PAGE 758
Functional description FTM counter MOD C(n+1)V C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 35-147. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V < C(n+1)V) FTM counter MOD = C(n+1)V C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 35-148.
PAGE 759
Chapter 35 FlexTimer Module (FTM) FTM counter MOD = C(n+1)V C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 not fully 100% duty cycle not fully 0% duty cycle Figure 35-150.
PAGE 760
Functional description FTM counter C(n+1)V MOD CNTIN C(n)V channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 35-152. Channel (n) output if C(n)V and C(n+1)V are not between CNTIN and MOD FTM counter MOD C(n+1)V = C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 35-153.
PAGE 761
Chapter 35 FlexTimer Module (FTM) FTM counter MOD C(n)V = C(n+1)V = CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 0% duty cycle 100% duty cycle Figure 35-154. Channel (n) output if (C(n)V = C(n+1)V = CNTIN) MOD = C(n+1)V = C(n)V FTM counter CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 0% duty cycle 100% duty cycle Figure 35-155.
PAGE 762
Functional description FTM counter MOD C(n+1)V CNTIN C(n)V channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 35-157. Channel (n) output if (C(n)V < CNTIN) and (CNTIN < C(n+1)V < MOD) FTM counter MOD C(n)V CNTIN C(n+1)V channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 35-158. Channel (n) output if (C(n+1)V < CNTIN) and (CNTIN < C(n)V < MOD) K20 Sub-Family Reference Manual, Rev.
PAGE 763
Chapter 35 FlexTimer Module (FTM) FTM counter C(n)V MOD C(n+1)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 35-159. Channel (n) output if (C(n)V > MOD) and (CNTIN < C(n+1)V < MOD) FTM counter C(n+1)V MOD C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 35-160. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V < MOD) K20 Sub-Family Reference Manual, Rev.
PAGE 764
Functional description FTM counter C(n+1)V MOD = C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 not fully 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 not fully 100% duty cycle Figure 35-161. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V = MOD) 35.4.8.
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Chapter 35 FlexTimer Module (FTM) channel (n+1) match FTM counter channel (n) match channel (n) output with ELSnB:ELSnA = 1:0 channel (n+1) output with COMP = 0 channel (n+1) output with COMP = 1 Figure 35-162. Channel (n+1) output in Complementary mode with (ELSnB:ELSnA = 1:0) channel (n+1) match FTM counter channel (n) match channel (n) output with ELSnB:ELSnA = X:1 channel (n+1) output with COMP = 0 channel (n+1) output with COMP = 1 Figure 35-163.
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Functional description 35.4.10.2 MOD register update The following table describes when MOD register is updated: Table 35-184. MOD register update When CLKS[1:0] = 0:0 Then MOD register is updated When MOD register is written, independent of FTMEN bit. • CLKS[1:0] ≠ 0:0, and • FTMEN = 0 According to the CPWMS bit, that is: • If the selected mode is not CPWM then MOD register is updated after MOD register was written and the FTM counter changes from MOD to CNTIN.
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Chapter 35 FlexTimer Module (FTM) 35.4.11 PWM synchronization The PWM synchronization provides an opportunity to update the MOD, CNTIN, CnV, OUTMASK, INVCTRL and SWOCTRL registers with their buffered value and force the FTM counter to the CNTIN register value. Note • The PWM synchronization must be used only in Combine mode. • The legacy PWM synchronization (SYNCMODE = 0) is a subset of the enhanced PWM synchronization (SYNCMODE = 1). Thus, only the enhanced PWM synchronization must be used. 35.4.11.
PAGE 768
Functional description system clock write 1 to TRIG0 bit TRIG0 bit trigger_0 input synchronized trigger_0 by system clock trigger 0 event Note All hardware trigger inputs have the same behavior. Figure 35-164. Hardware trigger event with HWTRIGMODE = 0 If HWTRIGMODE = 1, then the TRIGn bit is only cleared when 0 is written to it. NOTE The HWTRIGMODE bit must be 1 only with enhanced PWM synchronization (SYNCMODE = 1). 35.4.11.
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Chapter 35 FlexTimer Module (FTM) system clock write 1 to SWSYNC bit SWSYNC bit software trigger event PWM synchronization selected loading point Figure 35-165. Software trigger event 35.4.11.3 Boundary cycle and loading points The boundary cycle definition is important for the loading points for the registers MOD, CNTIN, and C(n)V. In Up counting mode, the boundary cycle is defined as when the counter wraps to its initial value (CNTIN).
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Functional description loading points if CNTMAX = 1 or CNTMIN = 1 CNT = MOD -> CNTIN up counting mode loading points if CNTMAX = 1 CNT = (MOD - 0x0001) -> MOD up-down counting mode CNT = (CNTIN + 0x0001) -> CNTIN loading points if CNTMIN = 1 Figure 35-166. Boundary cycles and loading points 35.4.11.4 MOD register synchronization The MOD register synchronization updates the MOD register with its buffer value. This synchronization is enabled if (FTMEN = 1).
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Chapter 35 FlexTimer Module (FTM) begin legacy PWM synchronization SYNCMODE bit ? =0 =1 enhanced PWM synchronization MOD register is updated by hardware trigger MOD register is updated by software trigger HWWRBUF = 0 bit ? SWWRBUF = 0 bit ? =1 =1 end software trigger 0= SWSYNC bit ? end hardware trigger TRIGn bit ? =1 =0 =1 FTM counter is reset by software trigger SWRSTCNT bit ? =1 wait hardware trigger n =0 wait the next selected loading point HWTRIGMODE bit ? =1 =0 update MOD w
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Functional description loading point. If the trigger event was a hardware trigger, then the trigger enable bit (TRIGn) is cleared according to Hardware trigger. Examples with software and hardware triggers follow. system clock write 1 to SWSYNC bit SWSYNC bit software trigger event selected loading point MOD register is updated Figure 35-168.
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Chapter 35 FlexTimer Module (FTM) system clock write 1 to SWSYNC bit SWSYNC bit software trigger event MOD register is updated Figure 35-170. MOD synchronization with (SYNCMODE = 0), (PWMSYNC = 0), (REINIT = 1), and software trigger was used system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event MOD register is updated Figure 35-171.
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Functional description 35.4.11.5 CNTIN register synchronization The CNTIN register synchronization updates the CNTIN register with its buffer value. This synchronization is enabled if (FTMEN = 1), (SYNCMODE = 1), and (CNTINC = 1). The CNTIN register synchronization can be done only by the enhanced PWM synchronization (SYNCMODE = 1). The synchronization mechanism is the same as the MOD register synchronization done by the enhanced PWM synchronization; see MOD register synchronization. 35.4.11.
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Chapter 35 FlexTimer Module (FTM) begin update OUTMASK register at each rising edge of system clock no = 0= SYNCHOM bit ? update OUTMASK register by PWM synchronization =1 1= rising edge of system clock ? SYNCMODE bit ? =0 legacy PWM synchronization = yes update OUTMASK with its buffer value end enhanced PWM synchronization OUTMASK is updated by hardware trigger OUTMASK is updated by software trigger 1= 0= SWSYNC bit ? SWOM bit ? software trigger =0 end 0= end HWOM bit ? =1 hardware t
PAGE 776
Functional description If (SYNCMODE = 0), (SYNCHOM = 1), and (PWMSYNC = 0), then this synchronization is done on the next enabled trigger event. If the trigger event was a software trigger, then the SWSYNC bit is cleared on the next selected loading point. If the trigger event was a hardware trigger, then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow.
PAGE 777
Chapter 35 FlexTimer Module (FTM) system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event OUTMASK register is updated and TRIG0 bit is cleared Figure 35-176. OUTMASK synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0), (SYNCHOM = 1), (PWMSYNC = 1), and a hardware trigger was used 35.4.11.8 INVCTRL register synchronization The INVCTRL register synchronization updates the INVCTRL register with its buffer value.
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Functional description begin update INVCTRL register at each rising edge of system clock 0= INVC bit ? =1 update INVCTRL register by PWM synchronization 1= no = rising edge of system clock ? SYNCMODE bit ? =0 end = yes update INVCTRL with its buffer value end enhanced PWM synchronization INVCTRL is updated by hardware trigger INVCTRL is updated by software trigger 1= 0= SWSYNC bit ? SWINVC bit ? software trigger =0 end 0= end HWINVC bit ? hardware trigger end TRIGn bit ? =0 =1 =1
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Chapter 35 FlexTimer Module (FTM) The SWOCTRL register can be updated at each rising edge of system clock (SWOC = 0) or by the enhanced PWM synchronization (SWOC = 1 and SYNCMODE = 1) according to the following flowchart. In the case of enhanced PWM synchronization, the SWOCTRL register synchronization depends on SWSOC and HWSOC bits.
PAGE 780
Functional description 35.4.11.10 FTM counter synchronization The FTM counter synchronization is a mechanism that allows the FTM to restart the PWM generation at a certain point in the PWM period. The channels outputs are forced to their initial value, except for channels in Output Compare mode, and the FTM counter is forced to its initial counting value defined by CNTIN register. The following figure shows the FTM counter synchronization.
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Chapter 35 FlexTimer Module (FTM) begin legacy PWM synchronization SYNCMODE bit ? =0 =1 enhanced PWM synchronization FTM counter is reset by software trigger SWSYNC bit ? SWRSTCNT bit ? software trigger =0 end =0 1= FTM counter is reset by hardware trigger end HWRSTCNT bit ? =1 hardware trigger =0 update the channels outputs with their initial value clear SWSYNC bit =0 =1 =1 update FTM counter with CNTIN register value TRIGn bit ? wait hardware trigger n update FTM counter with CN
PAGE 782
Functional description system clock write 1 to SWSYNC bit SWSYNC bit software trigger event FTM counter is updated with the CNTIN register value and channel outputs are forced to their initial value Figure 35-181. FTM counter synchronization with (SYNCMODE = 0), (REINIT = 1), (PWMSYNC = 0), and software trigger was used system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event FTM counter is updated with the CNTIN register value and channel outputs are forced to their initial value Figure 35-182.
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Chapter 35 FlexTimer Module (FTM) 35.4.12 Inverting The invert functionality swaps the signals between channel (n) and channel (n+1) outputs. The inverting operation is selected when (FTMEN = 1), (QUADEN = 0), (DECAPEN = 0), (COMBINE = 1), (COMP = 1), (CPWMS = 0), and (INVm = 1), where m represents a channel pair.
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Functional description channel (n+1) match FTM counter channel (n) match channel (n) output before the inverting channel (n+1) output before the inverting write 1 to INV(m) bit INV(m) bit buffer INVCTRL register synchronization INV(m) bit channel (n) output after the inverting channel (n+1) output after the inverting NOTE INV(m) bit selects the inverting to the pair channels (n) and (n+1). Figure 35-185.
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Chapter 35 FlexTimer Module (FTM) channel (n+1) match FTM counter channel (n) match channel (n) output after the software output control channel (n+1) output after the software output control CH(n)OC buffer CH(n+1)OC buffer write to SWOCTRL register write to SWOCTRL register CH(n)OC bit CH(n+1)OC bit SWOCTRL register synchronization SWOCTRL register synchronization NOTE CH(n)OCV = 1 and CH(n+1)OCV = 0. Figure 35-186.
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Functional description Note • The software output control feature must be used only in Combine mode. • The CH(n)OC and CH(n+1)OC bits should be equal. • The COMP bit must not be modified when software output control is enabled, that is, CH(n)OC = 1 and/or CH(n +1)OC = 1. • Software output control has the same behavior with disabled or enabled FTM counter (see the CLKS bitfield description in the Status and Control register). 35.4.
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Chapter 35 FlexTimer Module (FTM) channel (n+1) match FTM counter channel (n) match channel (n) output (before deadtime insertion) channel (n+1) output (before deadtime insertion) channel (n) output (after deadtime insertion) channel (n+1) output (after deadtime insertion) Figure 35-187.
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Functional description • and the deadtime delay is greater than or equal to the channel (n) duty cycle ((C(n +1)V – C(n)V) × system clock), then the channel (n) output is always the inactive value (POL(n) bit value). • and the deadtime delay is greater than or equal to the channel (n+1) duty cycle ((MOD – CNTIN + 1 – (C(n+1)V – C(n)V) ) × system clock), then the channel (n+1) output is always the inactive value (POL(n+1) bit value).
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Chapter 35 FlexTimer Module (FTM) 35.4.15 Output mask The output mask can be used to force channels output to their inactive state through software. For example: to control a BLDC motor. Any write to the OUTMASK register updates its write buffer. The OUTMASK register is updated with its buffer value by PWM synchronization; see OUTMASK register synchronization. If CHnOM = 1, then the channel (n) output is forced to its inactive state (POLn bit value).
PAGE 790
Functional description Note The output mask feature must be used only in Combine mode. 35.4.16 Fault control The fault control is enabled if (FTMEN = 1) and (FAULTM[1:0] ≠ 0:0). FTM can have up to four fault inputs. FAULTnEN bit (where n = 0, 1, 2, 3) enables the fault input n and FFLTRnEN bit enables the fault input n filter. FFVAL[3:0] bits select the value of the enabled filter in each enabled fault input.
PAGE 791
Chapter 35 FlexTimer Module (FTM) (FFVAL[3:0] 0000) and (FFLTRnEN*) FLTnPOL synchronizer fault input n* value 0 fault input n* system clock D CLK Q D Q CLK Fault filter (5-bit counter) 1 fault input polarity control rising edge detector FAULTFn* * where n = 3, 2, 1, 0 Figure 35-192. Fault input n control block diagram If the fault control and fault input n are enabled and a rising edge at the fault input n signal is detected, a fault condition has occurred and the FAULTFn bit is set.
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Functional description 35.4.16.1 Automatic fault clearing If the automatic fault clearing is selected (FAULTM[1:0] = 1:1), then the channels output disabled by fault control is again enabled when the fault input signal (FAULTIN) returns to zero and a new PWM cycle begins. See the following figure.
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Chapter 35 FlexTimer Module (FTM) the beginning of new PWM cycles FTM counter channel (n) output (before fault control) FAULTIN bit channel (n) output (after fault control with manual fault clearing and POLn=0) FAULTF bit FAULTF bit is cleared NOTE The channel (n) output is after the fault control with manual fault clearing and POLn = 0. Figure 35-195. Fault control with manual fault clearing 35.4.16.
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Functional description Note The polarity control must be used only in Combine mode. 35.4.18 Initialization The initialization forces the CHnOI bit value to the channel (n) output when a one is written to the INIT bit. The initialization depends on COMP and DTEN bits. The following table shows the values that channels (n) and (n+1) are forced by initialization when the COMP and DTEN bits are zero. Table 35-189.
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Chapter 35 FlexTimer Module (FTM) pair channels (m) - channels (n) and (n+1) FTM counter QUADEN DECAPEN COMBINE(m) CPWMS C(n)V MS(n)B CH(n)OC MS(n)A CH(n)OCV POL(n) ELS(n)B CH(n+1)OC POL(n+1) ELS(n)A CH(n)OI CH(n+1)OI COMP(m) INV(m)EN CH(n+1)OCV CH(n)OM DTEN(m) CH(n+1)OM FAULTEN(m) channel (n) output signal generation of channel (n) output signal initialization complementary mode inverting software output control deadtime insertion output mask fault control polarity control channel
PAGE 796
Functional description The FTM is able to generate multiple triggers in one PWM period. Because each trigger is generated for a specific channel, several channels are required to implement this functionality. This behavior is described in the following figure.
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Chapter 35 FlexTimer Module (FTM) • When there is the FTM counter synchronization • If (CNT = CNTIN), (CLKS[1:0] = 0:0), and a value different from zero is written to CLKS[1:0] bits The following figures show these cases. CNTIN = 0x0000 MOD = 0x000F CPWMS = 0 system clock FTM counter 0x0C 0x0D 0x0E 0x0F 0x00 0x01 0x02 0x03 0x04 0x05 initialization trigger Figure 35-198.
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Functional description CNTIN = 0x0000 MOD = 0x000F CPWMS = 0 system clock 0x00 FTM counter CLKS[1:0] bits 00 0x01 0x02 0x03 0x04 0x05 01 initialization trigger Figure 35-201. Initialization trigger is generated if (CNT = CNTIN), (CLKS[1:0] = 0:0), and a value different from zero is written to CLKS[1:0] bits The initialization trigger output provides a trigger signal that is used for on-chip modules. Note The initialization trigger must be used only in Combine mode. 35.4.
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Chapter 35 FlexTimer Module (FTM) FTM counter clock set CAPTEST clear CAPTEST write to MODE CAPTEST bit FTM counter 0x1053 0x1054 0x1055 0x1056 0x78AC 0x78AD 0x78AE0x78AF 0x78B0 write 0x78AC write to CNT CHnF bit 0x78AC 0x0300 CnV NOTE - FTM counter configuration: (FTMEN = 1), (QUADEN = 0), (CAPTEST = 1), (CPWMS = 0), (CNTIN = 0x0000), and (MOD = 0xFFFF) - FTM channel n configuration: input capture mode - (DECAPEN = 0), (COMBINE = 0), and (MSnB:MSnA = 0:0) Figure 35-202. Capture Test mode 35.
PAGE 800
Functional description Table 35-192. Clear CHnF bit when DMA = 1 CHnIE How CHnF Bit Can Be Cleared 0 CHnF bit is cleared either when the channel DMA transfer is done or by reading CnSC while CHnF is set and then writing a 0 to CHnF bit. 1 CHnF bit is cleared when the channel DMA transfer is done. 35.4.24 Dual Edge Capture mode The Dual Edge Capture mode is selected if FTMEN = 1 and DECAPEN = 1.
PAGE 801
Chapter 35 FlexTimer Module (FTM) The C(n)V register stores the value of FTM counter when the selected edge by channel (n) is detected at channel (n) input. The C(n+1)V register stores the value of FTM counter when the selected edge by channel (n+1) is detected at channel (n) input. In this mode, a coherency mechanism ensures coherent data when the C(n)V and C(n +1)V registers are read. The only requirement is that C(n)V must be read before C(n +1)V.
PAGE 802
Functional description 35.4.24.2 Continuous Capture mode The Continuous Capture mode is selected when (FTMEN = 1), (DECAPEN = 1), and (MS(n)A = 1). In this capture mode, the edges at the channel (n) input are captured continuously. The ELS(n)B:ELS(n)A bits select the initial edge to be captured, and ELS(n+1)B:ELS(n+1)A bits select the final edge to be captured. The edge captures are enabled while DECAP bit is set.
PAGE 803
Chapter 35 FlexTimer Module (FTM) 4 FTM counter 12 8 3 7 2 6 1 16 11 10 5 20 15 14 9 13 24 19 18 17 28 23 27 22 26 21 25 channel (n) input (after the filter channel input) DECAPEN bit set DECAPEN DECAP bit set DECAP C(n)V 1 3 5 7 9 15 2 4 6 8 10 16 19 CH(n)F bit clear CH(n)F C(n+1)V 20 22 24 CH(n+1)F bit clear CH(n+1)F problem 1 problem 2 Note - The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user.
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Functional description 4 FTM counter 12 8 3 7 2 6 1 16 11 10 5 20 15 14 9 13 24 19 18 17 28 23 27 22 26 21 25 channel (n) input (after the filter channel input) DECAPEN bit set DECAPEN DECAP bit set DECAP C(n)V 1 3 5 7 9 11 15 19 21 23 2 4 6 8 10 12 16 20 22 24 CH(n)F bit clear CH(n)F C(n+1)V CH(n+1)F bit clear CH(n+1)F Note - The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user. Figure 35-205.
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Chapter 35 FlexTimer Module (FTM) The following figure shows an example of the Dual Edge Capture – One-Shot mode used to measure the period between two consecutive rising edges. The DECAPEN bit selects the Dual Edge Capture mode, so it remains set. The DECAP bit is set to enable the measurement of next period. The CH(n)F bit is set when the first rising edge is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits.
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Functional description when the second rising edge is detected, that is, the edge selected by ELS(n+1)B:ELS(n +1)A bits. The CH(n+1)F bit indicates when two edges of the period were captured and the C(n)V and C(n+1)V registers are ready for reading.
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Chapter 35 FlexTimer Module (FTM) When a rising edge occurs in the channel (n) input signal, the FTM counter value is captured into channel (n) capture buffer. The channel (n) capture buffer value is transferred to C(n)V register when a falling edge occurs in the channel (n) input signal. C(n)V register has the FTM counter value when the previous rising edge occurred, and the channel (n) capture buffer has the FTM counter value when the last rising edge occurred.
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Functional description PHAFLTREN CH0FVAL[3:0] synchronizer CNTIN 0 phase A input system clock Q D CLK D PHAPOL 1 Filter CLK MOD filtered phase A signal Q PHBPOL FTM counter enable up/down FTM counter PHBFLTREN direction CH1FVAL[3:0] TOFDIR synchronizer QUADIR 0 phase B input Q D D Q filtered phase B signal CLK CLK Filter 1 Figure 35-209.
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Chapter 35 FlexTimer Module (FTM) phase B (counting direction) phase A (counting rate) FTM counter increment/decrement +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 FTM counter MOD CNTIN 0x0000 Time Figure 35-210. Quadrature Decoder – Count and Direction Encoding mode If QUADMODE = 0, then the Phase A and Phase B Encoding mode is enabled; see the following figure.
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Functional description phase A phase B FTM counter increment/decrement +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 FTM counter MOD CNTIN 0x0000 Time Figure 35-211. Quadrature Decoder – Phase A and Phase B Encoding mode The following figure shows the FTM counter overflow in up counting. In this case, when the FTM counter changes from MOD to CNTIN, TOF and TOFDIR bits are set. TOF bit indicates the FTM counter overflow occurred.
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Chapter 35 FlexTimer Module (FTM) phase A phase B FTM counter increment/decrement -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 FTM counter MOD CNTIN 0x0000 Time set TOF clear TOFDIR set TOF clear TOFDIR Figure 35-213. FTM counter overflow in down counting for Quadrature Decoder mode 35.4.25.1 Quadrature Decoder boundary conditions The following figures show the FTM counter responding to motor jittering typical in motor position control applications.
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Functional description phase A phase B FTM counter MOD CNTIN 0x0000 Time Figure 35-215. Motor position jittering near maximum and minimum count value The first highlighted transition causes a jitter on the FTM counter value near the maximum count value (MOD). The second indicated transition occurs on phase A and causes the FTM counter transition between the maximum and minimum count values which are defined by MOD and CNTIN registers.
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Chapter 35 FlexTimer Module (FTM) Table 35-193. FTM behavior when the chip Is in BDM mode (continued) BDMMODE 11 FTM Counter Functional mode CH(n)F Bit FTM Channels Output Writes to MOD, CNTIN, and C(n)V Registers can be set Functional mode Functional mode Note that if BDMMODE[1:0] = 2’b00 then the channels outputs remain at the value when the chip enters in BDM mode, because the FTM counter is stopped. However, the following situations modify the channels outputs in this BDM mode.
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Functional description FTM counter = MOD FTM counter = C7V FTM counter = C6V FTM counter = C5V FTM counter = C4V FTM counter = C3V FTM counter = C2V FTM counter = C1V FTM counter = C0V (a) (b) (c) (d) (e) (f) NOTE (a) LDOK = 0, CH0SEL = 0, CH1SEL = 0, CH2SEL = 0, CH3SEL = 0, CH4SEL = 0, CH5SEL = 0, CH6SEL = 0, CH7SEL = 0 (b) LDOK = 1, CH0SEL = 0, CH1SEL = 0, CH2SEL = 0, CH3SEL = 0, CH4SEL = 0, CH5SEL = 0, CH6SEL = 0, CH7SEL = 0 (c) LDOK = 0, CH0SEL = 0, CH1SEL = 0, CH2SEL = 0, CH3SEL = 1, CH4SEL = 0, CH5S
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Chapter 35 FlexTimer Module (FTM) then the generated signal is not available on channel (j) output. • If CHjIE = 1, then the channel (j) interrupt is generated when the channel (j) match occurs. • At the intermediate load neither the channels outputs nor the FTM counter are changed. Software must set the intermediate load at a safe point in time. • The intermediate load feature must be used only in Combine mode. 35.4.
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Reset overview gtb_out signals, represented by the example glue logic shown in the figure. Note that these configurations are chip-dependent and implemented outside of the FTM modules. See the chip configuration details for the chip's specific implementation. NOTE • In order to use the internal GTB signals to synchronize the FTM counter of different FTM modules, the configuration of each FTM module should guarantee that its FTM counter starts counting as soon as the gtb_in signal is 1.
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Chapter 35 FlexTimer Module (FTM) • • • • • • the timer overflow interrupt is zero, see Timer Overflow Interrupt; the channels interrupts are zero, see Channel (n) Interrupt; the fault interrupt is zero, see Fault Interrupt; the channels are in input capture mode, see Input Capture mode; the channels outputs are zero; the channels pins are not controlled by FTM (ELS(n)B:ELS(n)A = 0:0) (../dil/ FTM.xml#ModeSel1Table ). The following figure shows the FTM behavior after the reset.
PAGE 818
FTM Interrupts register (item 3). In this case, use the software output control (Software output control) or the initialization (Initialization) to update the channel output to the selected value (item 4). (4) use of software output control or initialization to update the channel output to the zero (1) FTM reset FTM counter CLKS[1:0] (3) write any value to CNT register XXXX 0x0000 XX 00 (5) write 1 to SC[CLKS] 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 . . .
PAGE 819
Chapter 36 Periodic Interrupt Timer (PIT) 36.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels. 36.1.1 Block diagram The following figure shows the block diagram of the PIT module. K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 Freescale Semiconductor, Inc.
PAGE 820
Signal description PIT Peripheral bus PIT registers load_value Timer 1 Iinterrupts Triggers Timer n Peripheral bus clock Figure 36-1. Block diagram of the PIT NOTE See the chip configuration details for the number of PIT channels used in this MCU. 36.1.2 Features The main features of this block are: • Ability of timers to generate DMA trigger pulses • Ability of timers to generate interrupts • Maskable interrupts • Independent timeout periods for each timer 36.
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Chapter 36 Periodic Interrupt Timer (PIT) 36.3 Memory map/register description This section provides a detailed description of all registers accessible in the PIT module. NOTE • Reserved registers will read as 0, writes will have no effect. • See the chip configuration details for the number of PIT channels used in this MCU. PIT memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_7000 PIT Module Control Register (PIT_MCR) 32 R/W 0000_0002h 36.3.
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Memory map/register description PIT memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4003_7138 Timer Control Register (PIT_TCTRL3) 32 R/W 0000_0000h 36.3.4/ 824 4003_713C Timer Flag Register (PIT_TFLG3) 32 R/W 0000_0000h 36.3.5/ 824 36.3.1 PIT Module Control Register (PIT_MCR) This register enables or disables the PIT timer clocks and controls the timers when the PIT enters the Debug mode.
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Chapter 36 Periodic Interrupt Timer (PIT) 36.3.2 Timer Load Value Register (PIT_LDVALn) These registers select the timeout period for the timer interrupts.
PAGE 824
Memory map/register description 36.3.4 Timer Control Register (PIT_TCTRLn) These registers contain the control bits for each timer.
PAGE 825
Chapter 36 Periodic Interrupt Timer (PIT) PIT_TFLGn field descriptions Field 31–1 Reserved 0 TIF Description This read-only field is reserved and always has the value zero. Timer Interrupt Flag Sets to 1 at the end of the timer period. Writing 1 to this flag clears it. Writing 0 has no effect. If enabled, or when TCTRLn[TIE] = 1, TIF causes an interrupt request. 0 1 Timeout has not yet occurred. Timeout has occurred. 36.
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Functional description Re-enable timer Disable timer Timer enabled Start value = p1 Trigger event p1 p1 p1 p1 Figure 36-23. Stopping and starting a timer The counter period of a running timer can be modified, by first disabling the timer, setting a new load value, and then enabling the timer again. See the following figure. Timer enabled Start value = p1 Re-enable Disable timer, Set new load value timer Trigger event p2 p1 p2 p2 p1 Figure 36-24.
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Chapter 36 Periodic Interrupt Timer (PIT) 36.4.2 Interrupts All the timers support interrupt generation. See the MCU specification for related vector addresses and priorities. Timer interrupts can be enabled by setting TCTRLn[TIE]. TFLGn[TIF] are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to the corresponding TFLGn[TIF]. 36.5 Initialization and application information In the example configuration: • The PIT clock has a frequency of 50 MHz.
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Initialization and application information PIT_LDVAL3 = 0x0016E35F; // setup timer 3for 1500000 cycles PIT_TCTRL3 |= TEN; // start Timer 3 K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 828 Freescale Semiconductor, Inc.
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Chapter 37 Low-Power Timer (LPTMR) 37.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. 37.1.
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LPTMR signal descriptions Table 37-1. Modes of operation Modes Description Run The LPTMR operates normally. Wait The LPTMR continues to operate normally and may be configured to exit the low-power mode by generating an interrupt request. Stop The LPTMR continues to operate normally and may be configured to exit the low-power mode by generating an interrupt request.
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Chapter 37 Low-Power Timer (LPTMR) 37.3 Memory map and register definition NOTE The LPTMR registers are reset only on a POR or LVD event. See LPTMR power and reset for more details. LPTMR memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4004_0000 Low Power Timer Control Status Register (LPTMR0_CSR) 32 R/W 0000_0000h 37.3.1/ 831 4004_0004 Low Power Timer Prescale Register (LPTMR0_PSR) 32 R/W 0000_0000h 37.3.
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Memory map and register definition LPTMRx_CSR field descriptions (continued) Field Description 0 1 6 TIE Timer Interrupt Enable When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set. 0 1 5–4 TPS Configures the input source to be used in Pulse Counter mode. TPS must be altered only when the LPTMR is disabled. The input connections vary by device. See the chip configuration details for information on the connections to these inputs.
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Chapter 37 Low-Power Timer (LPTMR) 37.3.
PAGE 834
Memory map and register definition LPTMRx_PSR field descriptions (continued) Field Description 2 PBYP Prescaler Bypass When PBYP is set, the selected prescaler clock in Time Counter mode or selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP must be altered only when the LPTMR is disabled. 0 1 1–0 PCS Prescaler/glitch filter is enabled. Prescaler/glitch filter is bypassed.
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Chapter 37 Low-Power Timer (LPTMR) 37.3.
PAGE 836
Functional description In Pulse Counter mode with the prescaler/glitch filter bypassed, the selected input source directly clocks the CNR and no other clock source is required. To minimize power in this case, configure the prescaler clock source for a clock that is not toggling. NOTE The clock source or pulse input source selected for the LPTMR should not exceed the frequency fLPTMR defined in the device datasheet. 37.4.
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Chapter 37 Low-Power Timer (LPTMR) 37.4.3.3 Glitch filter In Pulse Counter mode, when the glitch filter is enabled, the output of the glitch filter directly clocks the CNR. When the LPTMR is first enabled, the output of the glitch filter is asserted, that is, logic 1 for active-high and logic 0 for active-low. The following table shows the change in glitch filter output with the selected input source.
PAGE 838
Functional description 37.4.5 LPTMR counter The CNR increments by one on every: • • • • Prescaler clock in Time Counter mode with prescaler bypassed Prescaler output in Time Counter mode with prescaler enabled Input source assertion in Pulse Counter mode with glitch filter bypassed Glitch filter output in Pulse Counter mode with glitch filter enabled The CNR is reset when the LPTMR is disabled or if the counter register overflows. If CSR[TFC] is set, then the CNR is also reset whenever CSR[TCF] is set.
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Chapter 38 Carrier Modulator Transmitter (CMT) 38.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The carrier modulator transmitter (CMT) module provides the means to generate the protocol timing and carrier signals for a wide variety of encoding schemes.
PAGE 840
Block diagram • Baseband • Frequency-shift key (FSK) • Direct software control of the IRO signal • Extended space operation in Time, Baseband, and FSK modes • Selectable input clock divider • Interrupt on end-of-cycle • Ability to disable the IRO signal and use as timer interrupt 38.3 Block diagram The following figure presents the block diagram of the CMT module. K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 840 Freescale Semiconductor, Inc.
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Chapter 38 Carrier Modulator Transmitter (CMT) CMT Carrier generator Modulator CMT_IRO CMT Interrupts CMT registers divider_enable Clock divider Peripheral bus clock Peripheral bus Figure 38-1. CMT module block diagram 38.4 Modes of operation The following table describes the operation of the CMT module operates in various modes. Table 38-1.
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Modes of operation Table 38-1. Modes of operation (continued) Modes Description Frequency-shift key This mode allows the carrier generator to alternate between two sets of high and low times. When operating in FSK mode, the generator will toggle between the two sets when instructed by the modulator, allowing the user to dynamically switch between two carrier frequencies without CPU intervention. The following table summarizes the modes of operation of the CMT module. Table 38-2.
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Chapter 38 Carrier Modulator Transmitter (CMT) 38.4.1 Wait mode operation During Wait mode, the CMT if enabled, will continue to operate normally. However, there is no change in operating modes of CMT during Wait mode, because the CPU is not operating. 38.4.2 Stop mode operation This section describes the CMT Stop mode operations. 38.4.2.1 Normal Stop mode operation During Normal Stop mode, clocks to the CMT module are halted. No registers are affected.
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Memory map/register definition 38.5.1 CMT_IRO — Infrared Output This output signal is driven by the modulator output when MSC[MCGEN] and OC[IROPEN] are set. The IRO signal starts a valid transmission with a delay, after MSC[MCGEN] bit be asserted to high, that can be calculated based on two register bits. Table 38-5 shows how to calculate this delay. The following table describes conditions for the IRO signal to be active.
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Chapter 38 Carrier Modulator Transmitter (CMT) CMT memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4006_2003 CMT Carrier Generator Low Data Register 2 (CMT_CGL2) 8 R/W Undefined 38.6.4/ 847 4006_2004 CMT Output Control Register (CMT_OC) 8 R/W 00h 38.6.5/ 848 4006_2005 CMT Modulator Status and Control Register (CMT_MSC) 8 R/W 00h 38.6.6/ 849 4006_2006 CMT Modulator Data Register Mark High (CMT_CMD1) 8 R/W Undefined 38.
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Memory map/register definition CMT_CGH1 field descriptions (continued) Field Description be written to nonzero values before the carrier generator is enabled to avoid spurious results. 38.6.2 CMT Carrier Generator Low Data Register 1 (CMT_CGL1) This data register contains the primary low value for generating the carrier output. Address: CMT_CGL1 is 4006_2000h base + 1h offset = 4006_2001h Bit 7 Read Write Reset 6 5 4 3 2 1 0 x* x* x* x* PL x* x* x* x* * Notes: • x = Undefined at reset.
PAGE 847
Chapter 38 Carrier Modulator Transmitter (CMT) CMT_CGH2 field descriptions Field Description 7–0 SH Secondary Carrier High Time Data Value Contains the number of input clocks required to generate the carrier high time period. When operating in Time mode, this register is never selected. When operating in FSK mode, this register and the primary register pair are alternately selected under control of the modulator. The secondary carrier high time value is undefined out of reset.
PAGE 848
Memory map/register definition 38.6.5 CMT Output Control Register (CMT_OC) This register is used to control the IRO signal of the CMT module. Address: CMT_OC is 4006_2000h base + 4h offset = 4006_2004h Bit Read Write Reset Bit Read Write Reset 7 6 5 4 0 IROL CMTPOL IROPEN 0 0 0 0 3 2 1 0 0 0 0 0 0 CMT_OC field descriptions Field 7 IROL 6 CMTPOL Description IRO Latch Control Reads the state of the IRO latch.
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Chapter 38 Carrier Modulator Transmitter (CMT) 38.6.6 CMT Modulator Status and Control Register (CMT_MSC) This register contains the modulator and carrier generator enable (MCGEN), end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle (EOCF) status bit.
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Memory map/register definition CMT_MSC field descriptions (continued) Field 4 EXSPC Description Extended Space Enable Enables the extended space operation. 0 Extended space is disabled. 1 Extended space is enabled. 3 BASE Baseband Enable When set, BASE disables the carrier generator and forces the carrier output high for generation of baseband protocols.
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Chapter 38 Carrier Modulator Transmitter (CMT) 38.6.7 CMT Modulator Data Register Mark High (CMT_CMD1) The contents of this register are transferred to the modulator down counter upon the completion of a modulation period. Address: CMT_CMD1 is 4006_2000h base + 6h offset = 4006_2006h Bit Read Write Reset 7 6 5 4 3 2 1 0 x* x* x* x* MB[15:8] x* x* x* x* * Notes: • x = Undefined at reset.
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Memory map/register definition 38.6.9 CMT Modulator Data Register Space High (CMT_CMD3) The contents of this register are transferred to the space period register upon the completion of a modulation period. Address: CMT_CMD3 is 4006_2000h base + 8h offset = 4006_2008h Bit Read Write Reset 7 6 5 4 3 2 1 0 x* x* x* x* SB[15:8] x* x* x* x* * Notes: • x = Undefined at reset.
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Chapter 38 Carrier Modulator Transmitter (CMT) 38.6.11 CMT Primary Prescaler Register (CMT_PPS) This register is used to set the Primary Prescaler Divider field (PPSDIV). Address: CMT_PPS is 4006_2000h base + Ah offset = 4006_200Ah Bit Read Write Reset 7 6 5 4 3 2 0 0 1 0 0 0 PPSDIV 0 0 0 0 0 CMT_PPS field descriptions Field 7–4 Reserved 3–0 PPSDIV Description This read-only field is reserved and always has the value zero.
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Functional description 38.6.12 CMT Direct Memory Access Register (CMT_DMA) This register is used to enable/disable direct memory access (DMA). Address: CMT_DMA is 4006_2000h base + Bh offset = 4006_200Bh Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 DMA 0 0 0 0 0 CMT_DMA field descriptions Field 7–1 Reserved 0 DMA Description This read-only field is reserved and always has the value zero. DMA Enable Enables the DMA protocol. 0 1 DMA transfer request and done are disabled.
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Chapter 38 Carrier Modulator Transmitter (CMT) Bus clock Primary prescaler if_clk_enable divider_enable Secondary prescaler Figure 38-14. Clock divider block diagram For compatibility with previous versions of CMT, when bus clock = 8 MHz, the PPS must be configured to zero. The PPS counter is selected according to the bus clock to generate an intermediate frequency approximately equal to 8 MHz. 38.7.
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Functional description For low-frequency signals with large periods, high-resolution duty cycles as a percentage of the total period, are possible. The carrier signal is generated by counting a register-selected number of input clocks (125 ns for an 8 MHz bus) for both the carrier high time and the carrier low time. The period is determined by the total number of clocks counted. The duty cycle is determined by the ratio of high-time clocks to total clocks counted.
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Chapter 38 Carrier Modulator Transmitter (CMT) Assuming that the high time count compare register is currently active, a valid compare will cause the carrier output to be driven low. The counter will continue to increment starting at the reset value of 0x01. When the value stored in the selected low count value register is reached, the counter will again be reset and the carrier output will be driven high. The cycle repeats, automatically generating a periodic signal which is directed to the modulator.
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Functional description Table 38-20. Mode functions (continued) Mode Function FSK The modulator can count carrier periods and instruct the carrier generator to alternate between two carrier frequencies whenever a modulation period consisting of mark and space counts, expires. The modulator provides a simple method to control protocol timing. The modulator has a minimum resolution of 1.0 μs with an 8 MHz. It can count bus clocks to provide realtime control, or carrier clocks for self-clocked protocols.
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Chapter 38 Carrier Modulator Transmitter (CMT) 16 bits 0 Mode CMTCMD1:CMTCMD2 CMTCLK 8 Clock control Counter MS bit 17-bit down counter * 16 Load =? Carrier out (fcg) Modulator gate System control EOC Flag set Module interrupt request Primary/Secondary select EOCIE EXSPC BASE Space period register FSK 16 Modulator out CMTCMD3:CMTCMD4 16 bits * Denotes hidden register Figure 38-16. Modulator block diagram 38.7.3.
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Functional description CMTCLK 8 Carrier out (fcg) Modulator gate Mark Space Mark IRO signal (Time mode) IRO signal (Baseband mode) Figure 38-17. Example: CMT output in Time and Baseband modes with OC[CMTPOL]=0 38.7.3.2 Baseband mode Baseband mode, that is, when MSC[MCGEN] and MSC[BASE] are set, is a derivative of Time mode, where the mark and space period is based on (CMTCLK ÷ 8) counts. The mark and space calculations are the same as in Time mode.
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Chapter 38 Carrier Modulator Transmitter (CMT) • The modulation mark and space periods consist of an integer number of carrier clocks (space period can be zero). • When the mark period expires, the space period is transparently started as in Time mode. • The carrier generator toggles between primary and secondary data register values whenever the modulator space period expires. The space period provides an interpulse gap (no carrier).
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Functional description 38.7.4 Extended space operation In either Time, Baseband, or FSK mode, the space period can be made longer than the maximum possible value of the space period register. Setting MSC[EXSPC] will force the modulator to treat the next modulation period beginning with the next load of the counter and space period register, as a space period equal in length to the mark and space counts combined.
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Chapter 38 Carrier Modulator Transmitter (CMT) CPU. If necessary, software must maintain tracking of the current primary or secondary modulation cycle. The extended space period ends at the completion of the space period time of the modulation period during which MSC[EXSPC]is cleared. The following table depicts the equations which can be used to calculate the extended space period depending on when MSC[EXSPC] is set.
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CMT interrupts and DMA When MSC[MCGEN] becomes disabled, the CMT module does not set MSC[EOCF] at the end of the last modulation cycle. If MSC[EOCIE] is high when MSC[EOCF] is set, the CMT module will generate an interrupt request or a DMA transfer request. MSC[EOCF] must be cleared to prevent from being generated by another event like interrupt or DMA request, after exiting the service routine. See the following table. Table 38-24.
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Chapter 39 Real Time Clock (RTC) 39.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 39.1.1 Features The RTC module features include: • Independent power supply, POR and 32 kHz crystal oscillator • 32-bit seconds counter with roll-over protection and 32-bit alarm • 16-bit prescaler with compensation that can correct errors between 0.
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Register definition During chip power-down, RTC is powered from the backup power supply (VBAT) and is electrically isolated from the rest of the chip but continues to increment the time counter (if enabled) and retain the state of the RTC registers. The RTC registers are not accessible. During chip power-up, RTC remains powered from the backup power supply (VBAT). All RTC registers are accessible by software and all functions are operational. If enabled, the 32.
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Chapter 39 Real Time Clock (RTC) Write accesses to any register by non-supervisor mode software, when the supervisor access bit in the control register is clear, will terminate with a bus error. Read accesses by non-supervisor mode software complete as normal. Writing to a register protected by the write access register or lock register does not generate a bus error, but the write will not complete.
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Register definition RTC_TSR field descriptions Field Description 31–0 TSR Time Seconds Register When the time counter is enabled, the TSR is read only and increments once a second provided SR[TOF] or SR[TIF] are not set. The time counter will read as zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the TSR can be read or written. Writing to the TSR when the time counter is disabled will clear the SR[TOF] and/or the SR[TIF].
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Chapter 39 Real Time Clock (RTC) 39.2.
PAGE 870
Register definition 39.2.
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Chapter 39 Real Time Clock (RTC) RTC_CR field descriptions (continued) Field Description 0 1 8 OSCE The 32kHz clock is output to other peripherals The 32kHz clock is not output to other peripherals Oscillator Enable 0 1 7–4 Reserved 32.768 kHz oscillator is disabled. 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. This read-only field is reserved and always has the value zero.
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Register definition RTC_SR field descriptions Field Description 31–5 Reserved This read-only field is reserved and always has the value zero. 4 TCE Time Counter Enable When time counter is disabled the TSR register and TPR register are writeable, but do not increment. When time counter is enabled the TSR register and TPR register are not writeable, but increment. 0 1 3 Reserved Time counter is disabled. Time counter is enabled. This read-only field is reserved and always has the value zero.
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Chapter 39 Real Time Clock (RTC) RTC_LR field descriptions Field Description 31–8 Reserved This read-only field is reserved and always has the value zero. 7 Reserved This read-only field is reserved and always has the value one. 6 LRL Lock Register Lock Once cleared, this bit can only be set by VBAT POR or software reset. 0 1 5 SRL Status Register Lock Once cleared, this bit can only be set by VBAT POR or software reset. 0 1 4 CRL Once cleared, this bit can only be set by VBAT POR.
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Register definition 39.2.
PAGE 875
Chapter 39 Real Time Clock (RTC) RTC_IER field descriptions (continued) Field Description 0 1 Time invalid flag does not generate an interrupt. Time invalid flag does generate an interrupt. 39.2.
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Register definition RTC_WAR field descriptions (continued) Field Description 0 1 2 TARW Writes to the time compensation register are ignored. Writes to the time compensation register complete as normal. Time Alarm Register Write Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset. 0 1 1 TPRW Writes to the time alarm register are ignored. Writes to the time alarm register complete as normal.
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Chapter 39 Real Time Clock (RTC) RTC_RAR field descriptions (continued) Field Description 0 1 5 SRR Status Register Read Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset. 0 1 4 CRR Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset. Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset Once cleared, this bit is only set by system reset.
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Functional description 39.3.1 Power, clocking and reset The RTC is an always powered block that is powered by the battery power supply (VBAT). The battery power supply ensures that the RTC registers retain their state during chip power-down and that the RTC time counter remains operational. The time counter within the RTC is clocked by a 32.768 kHz clock and can supply this clock to other peripherals. The 32.
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Chapter 39 Real Time Clock (RTC) 39.3.2 Time counter The time counter consists of a 32-bit seconds counter that increments once every second and a 16-bit prescaler register that increments once every 32.768 kHz clock cycle. The time seconds register and time prescaler register can only be written when the SR[TCE] bit is clear. Always write to the prescaler register before writing to the seconds register, since the seconds register increments on the falling edge of bit 14 of the prescaler register.
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Functional description Cycles are added or subtracted from the prescaler register when the prescaler register equals 0x3FFF and then increments. The compensation interval is used to adjust the frequency at which the time compensation value is used (from once a second to once every 256 seconds). Updates to the time compensation register will not take effect until the next time the time seconds register increments and provided the previous compensation interval has expired.
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Chapter 39 Real Time Clock (RTC) 39.3.6 Register lock The lock register can be used to block write accesses to certain registers until the next VBAT POR or software reset. Locking the control register will disable the software reset. Locking the lock register will block future updates to the lock register. Write accesses to a locked register are ignored and do not generate a bus error. 39.3.
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Functional description K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 882 Freescale Semiconductor, Inc.
PAGE 883
Chapter 40 Universal Serial Bus OTG Controller (USBOTG) 40.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This section describes the USB. The OTG implementation in this module provides limited host functionality and device solutions for implementing a USB 2.0 full-speed/ low-speed compliant peripheral. The OTG implementation supports the On-The-Go (OTG) addendum to the USB 2.0 Specification.
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Introduction The host initiates transactions to specific peripherals, whereas the device responds to control transactions. The device sends and receives data to and from the host using a standard USB data format. USB 2.0 full-speed /low-speed peripherals operate at 12Mbit/s or 1.5 Mbit/s. For additional information, see the USB 2.0 specification. Host PC External Hub External Hub Root Hub Host Software USB Cable USB Cable USB Cables USB Cable USB Peripherals Figure 40-1. Example USB 2.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) Print Photos Keyboard Input Swap Songs Hot Sync Figure 40-2. Example USB 2.0 On-The-Go configurations 40.1.3 USB-FS Features • USB 1.1 and 2.0 compliant full-speed device controller • 16 bidirectional end points • DMA or FIFO data stream interfaces • Low-power consumption • On-The-Go protocol logic 40.2 Functional description The USB-FS 2.
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Programmers interface 40.2.1 Data Structures The function of the device operation is to transfer a request in the memory image to and from the Universal Serial Bus. To efficiently manage USB endpoint communications the USB-FS implements a Buffer Descriptor Table (BDT) in system memory. See Figure 40-3. 40.3 Programmers interface This section discusses the major components of the programming model for the USB module. 40.3.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) System Memory BDT_PAGE Registers END_POINT IN ODD 000 BDT Page Current Endpoint BDT ••• Start of Buffer ••• Buffer in Memory Figure 40-3. Buffer descriptor table 40.3.2 RX vs.
PAGE 888
Programmers interface 40.3.3 Addressing BDT entries An understanding of the addressing mechanism of the Buffer Descriptor Table is useful when accessing endpoint data via the USB-FS or microprocessor. Some points of interest are: • • • • • • • The BDT occupies up to 512 bytes of system memory. 16 bidirectional endpoints can be supported with a full BDT of 512 bytes. 16 bytes are needed for each USB endpoint direction. Applications with less than 16 endpoints require less RAM to implement the BDT.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) • Who owns the buffer in system memory • Data0 or Data1 PID • Whether to release ownership upon packet completion • No address increment (FIFO mode) • Whether data toggle synchronization is enabled • How much data is to be transmitted or received • Where the buffer resides in system memory While the processor uses the data stored in the BDs to determine: • Who owns the buffer in system memory • Data0 or Data1 PID • The received TOKEN PID • How much da
PAGE 890
Programmers interface Table 40-4. Buffer descriptor fields (continued) Field 7 OWN Description Determines whether the processor or the USB-FS currently owns the buffer. Except when KEEP=1, the SIE writes a 0 to this bit when it has completed a token. This must always be the last byte of the BD that the processor updates when it initializes a BD. 0 The processor has exclusive access to the BD. The USB-FS ignores all other fields in the BD. 1 USB-FS has exclusive access to the BD.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) Table 40-4. Buffer descriptor fields (continued) Field TOK_PID[n] Description Bits [5:2] can also represent the current token PID. The current token PID is written back in to the BD by the USB-FS when a transfer completes. The values written back are the token PID values from the USB specification: • 0x1 for an OUT token. • 0x9 for an IN token. • 0xd for a SETUP token.
PAGE 892
Programmers interface USB RST SOF USB_RST Interrupt Generated SOF Interrupt Generated SETUP TOKEN DATA ACK TOK_DNE Interrupt Generated DATA IN TOKEN ACK TOK_DNE Interrupt Generated OUT TOKEN DATA USB Host ACK TOK_DNE Interrupt Generated Function Figure 40-4. USB token transaction The USB has two sources for the DMA overrun error: Memory Latency The memory latency may be too high and cause the receive FIFO to overflow.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) Table 40-5. USB responses to DMA overrun errors (continued) Errors due to Memory Latency Errors due to Oversized Packets • For host mode, the TOKDNE interrupt is generated and The packet length field written back to the BDT is the the TOK_PID field of the BDT is 1111 to indicate the MaxPacket value that represents the length of the clipped DMA latency error. Host mode software can decide to data actually written to memory.
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Memory map/Register definitions USB memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4007_2088 Error Interrupt Status Register (USB0_ERRSTAT) 8 R/W 00h 40.4.11/ 903 4007_208C Error Interrupt Enable Register (USB0_ERREN) 8 R/W 00h 40.4.12/ 904 4007_2090 Status Register (USB0_STAT) 8 R 00h 40.4.13/ 906 4007_2094 Control Register (USB0_CTL) 8 R/W 00h 40.4.14/ 907 4007_2098 Address Register (USB0_ADDR) 8 R/W 00h 40.4.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) USB memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_20E0 Endpoint Control Register (USB0_ENDPT8) 8 R/W 00h 40.4.23/ 912 4007_20E4 Endpoint Control Register (USB0_ENDPT9) 8 R/W 00h 40.4.23/ 912 4007_20E8 Endpoint Control Register (USB0_ENDPT10) 8 R/W 00h 40.4.23/ 912 4007_20EC Endpoint Control Register (USB0_ENDPT11) 8 R/W 00h 40.4.
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Memory map/Register definitions USBx_PERID field descriptions Field 7–6 Reserved 5–0 ID Description This read-only field is reserved and always has the value zero. Peripheral Identification This field always reads 0x4h. 40.4.2 Peripheral ID Complement register (USBx_IDCOMP) Reads back the complement of the Peripheral ID register. For the USB peripheral, the value is 0xFB.
PAGE 897
Chapter 40 Universal Serial Bus OTG Controller (USBOTG) 40.4.4 Peripheral Additional Info register (USBx_ADDINFO) Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with the Host Enable bit.
PAGE 898
Memory map/Register definitions USBx_OTGISTAT field descriptions (continued) Field 4 Reserved Description This read-only field is reserved and always has the value zero. 3 SESSVLDCHG This bit is set when a change in VBUS is detected indicating a session valid or a session no longer valid. 2 B_SESS_CHG This bit is set when a change in VBUS is detected on a B device. 1 Reserved 0 AVBUSCHG This read-only field is reserved and always has the value zero.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) USBx_OTGICR field descriptions (continued) Field Description 2 BSESSEN B Session END Interrupt Enable 1 Reserved This read-only field is reserved and always has the value zero. 0 AVBUSEN A VBUS Valid Interrupt Enable 0 1 0 1 Disables the B_SESS_CHG interrupt. Enables the B_SESS_CHG interrupt. Disables the AVBUSCHG interrupt. Enables the AVBUSCHG interrupt. 40.4.
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Memory map/Register definitions USBx_OTGSTAT field descriptions (continued) Field Description 3 SESS_VLD Session Valid 2 BSESSEND B Session End 0 1 0 1 1 Reserved The VBUS voltage is below the B session valid threshold The VBUS voltage is above the B session valid threshold. The VBUS voltage is above the B session end threshold. The VBUS voltage is below the B session end threshold. This read-only field is reserved and always has the value zero.
PAGE 901
Chapter 40 Universal Serial Bus OTG Controller (USBOTG) USBx_OTGCTL field descriptions (continued) Field Description 0 1 3 Reserved 2 OTGEN This read-only field is reserved and always has the value zero. On-The-Go pullup/pulldown resistor enable 0 1 1–0 Reserved D- pulldown resistor is not enabled. D- pulldown resistor is enabled. If USB_EN is set and HOST_MODE is clear in the Control Register (CTL), then the D+ Data Line pullup resistors are enabled.
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Memory map/Register definitions USBx_ISTAT field descriptions (continued) Field Description 4 SLEEP This bit is set when the USB Module detects a constant idle on the USB bus for 3 milliseconds. The sleep timer is reset by activity on the USB bus. 3 TOKDNE This bit is set when the current token being processed has completed. The processor should immediately read the STAT register to determine the EndPoint and BD used for this token.
PAGE 903
Chapter 40 Universal Serial Bus OTG Controller (USBOTG) USBx_INTEN field descriptions (continued) Field 4 SLEEPEN Description SLEEP Interrupt Enable 0 1 The SLEEP interrupt is not enabled. The SLEEP interrupt is enabled. 3 TOKDNEEN TOKDNE Interrupt Enable 2 SOFTOKEN SOFTOK Interrupt Enable 1 ERROREN ERROR Interrupt Enable 0 USBRSTEN USBRST Interrupt Enable 0 1 0 1 0 1 0 1 The TOKDNE interrupt is not enabled. The TOKDNE interrupt is enabled. The SOFTOK interrupt is not enabled.
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Memory map/Register definitions USBx_ERRSTAT field descriptions (continued) Field Description 6 Reserved This read-only field is reserved and always has the value zero. 5 DMAERR This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data. If processing a TX transfer this would cause a transmit data underflow condition. If processing a RX transfer this would cause a receive data overflow condition.
PAGE 905
Chapter 40 Universal Serial Bus OTG Controller (USBOTG) USBx_ERREN field descriptions Field 7 BTSERREN 6 Reserved Description BTSERR Interrupt Enable 0 1 The BTSERR interrupt is not enabled. The BTSERR interrupt is enabled. This read-only field is reserved and always has the value zero. 5 DMAERREN DMAERR Interrupt Enable 4 BTOERREN BTOERR Interrupt Enable 3 DFN8EN 2 CRC16EN 1 CRC5EOFEN 0 PIDERREN 0 1 0 1 The DMAERR interrupt is not enabled. The DMAERR interrupt is enabled.
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Memory map/Register definitions 40.4.13 Status Register (USBx_STAT) The Status Register reports the transaction status within the USB Module. When the processor's interrupt controller has received a TOKDNE interrupt the Status Register should be read to determine the status of the previous endpoint communication. The data in the status register is valid when the TOKDNE interrupt bit is asserted. The STAT register is actually a read window into a status FIFO maintained by the USB Module.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) 40.4.14 Control Register (USBx_CTL) The Control Register provides various control and configuration information for the USB Module.
PAGE 908
Memory map/Register definitions USBx_CTL field descriptions (continued) Field Description Setting this bit causes the SIE to reset all of its ODD bits to the BDTs. Therefore, setting this bit resets much of the logic in the SIE. When host mode is enabled, clearing this bit causes the SIE to stop sending SOF tokens. 0 The USB Module is disabled. 1 The USB Module is enabled. 40.4.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) 40.4.16 BDT Page Register 1 (USBx_BDTPAGE1) The Buffer Descriptor Table Page Register 1 provides address bits 15 through 9 of the base address where the current Buffer Descriptor Table (BDT) resides in system memory. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so bits 8 through 0 of the base address are always taken as zero.
PAGE 910
Memory map/Register definitions 40.4.18 Frame Number Register High (USBx_FRMNUMH) The Frame Number Register (Low and High) contains an 11-bit value used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory.
PAGE 911
Chapter 40 Universal Serial Bus OTG Controller (USBOTG) USBx_TOKEN field descriptions Field 7–4 TOKENPID 3–0 TOKENENDPT Description This 4-bit field contains the token type executed by the USB Module. 0001 1001 1101 OUT Token. USB Module performs an OUT (TX) transaction. IN Token. USB Module performs an In (RX) transaction. SETUP Token. USB Module performs a SETUP (TX) transaction This 4 bit field holds the Endpoint address for the token command. The four bit value written must be a valid endpoint.
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Memory map/Register definitions 40.4.21 BDT Page Register 2 (USBx_BDTPAGE2) The Buffer Descriptor Table Page Register 2 contains an 8-bit value used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) In Host mode ENDPT0 is used to determine the handshake, retry and low speed characteristics of the host transfer. For Host mode control, bulk and interrupt transfers the EPHSHK bit should be set to 1. For Isochronous transfers it should be set to 0. Common values to use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers, and 0x4C for Isochronous transfers.
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Memory map/Register definitions USBx_USBCTRL field descriptions Field 7 SUSP 6 PDE 5–0 Reserved Description Places the USB transceiver into the suspend state. 0 1 USB transceiver is not in suspend state. USB transceiver is in suspend state. Enables the weak pulldowns on the USB transceiver. 0 1 Weak pulldowns are disabled on D+ and DWeak pulldowns are enabled on D+ and D-. This read-only field is reserved and always has the value zero. 40.4.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) 40.4.26 USB OTG Control Register (USBx_CONTROL) Addresses: USB0_CONTROL is 4007_2000h base + 108h offset = 4007_2108h Bit 7 6 Read Write Reset 0 0 Bit 3 2 5 0 Read Write Reset 4 DPPULLUPNONOTG 0 0 1 0 0 0 0 0 0 USBx_CONTROL field descriptions Field Description 7–5 Reserved This read-only field is reserved and always has the value zero.
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Memory map/Register definitions USBx_USBTRC0 field descriptions (continued) Field Description NOTE: It is always read as zero. 0 1 6 Reserved 5 USBRESMEN This read-only field is reserved and always has the value zero. Asynchronous Resume Interrupt Enable This bit, when set, allows the USB module to send an asynchronous wakeup event to the MCU upon detection of resume signaling on the USB bus. The MCU then re-enables clocks to the USB module.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) 40.5 OTG and Host Mode Operation The Host Mode logic allows devices such as digital cameras and palmtop computers to function as a USB Host Controller. The OTG logic adds an interface to allow the OTG Host Negotiation and Session Request Protocols (HNP and SRP) to be implemented in software. Host Mode allows a peripheral such as a digital camera to be connected directly to a USB compliant printer.
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Host Mode Operation Examples 2. Enable the ATTACH interrupt (INT_ENB[ATTACH]=1). 3. Wait for ATTACH interrupt (INT_STAT[ATTACH]). Signaled by USB Target pullup resistor changing the state of DPLUS or DMINUS from 0 to 1 (SE0 to J or K state). 4. Check the state of the JSTATE and SE0 bits in the control register.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) complete. When the BDT is written a token done (INT_STAT[TOK_DNE]) interrupt is asserted. This completes the setup phase of the setup transaction. Refer to the Universal Serial Bus Revision 2.0 specification, "Chapter 9 USB Device Framework" (http://www.usb.org/developers/docs). 7.
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On-The-Go Operation 1. Complete all steps discover a connected device and to configure a connected device. Write the ADDR register with the address of the target device. Typically, there is only one other device on the USB bus in host mode so it is expected that the address is 0x01 and should remain constant. 2. Write the ENDPT0 to 0x1D register to enable transmit and receive transfers with handshaking enabled. 3. Setup the Even TX EP0 BDT to transfer up to 64 bytes. 4.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) 40.7.1 OTG Dual Role A Device Operation A device is considered the A device because of the type of cable attached. If the USB Type A connector or the USB Type Mini A connector is plugged into the device, he is considered the A device. A dual role A device operates as the following flow diagram and state description table illustrates. A_IDLE B_IDLE A_WAIT_VFALL A_WAIT_VRISE A_PERIPHERAL A_WAIT_BCON A_SUSPEND A_HOST Figure 40-93.
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On-The-Go Operation Table 40-96. State Descriptions for the Dual Role A Device Flow (continued) State Action Response A_WAIT_BCON After 200 msec without Attach or ID Interrupt. (This could wait forever if desired.) Go to A_WAIT_FALL A_VBUS_VLD Interrupt and B device attaches Go to A_HOST Turn off DRV_VBUS Turn on Host Mode A_HOST Enumerate Device determine OTG Support.
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Chapter 40 Universal Serial Bus OTG Controller (USBOTG) B_IDLE A_IDLE B_HOST B_WAIT_ACON B_SRP_INIT B_PERIPHERAL Figure 40-94. Dual Role B Device Flow Diagram Table 40-97. State Descriptions for the Dual Role B Device Flow State Action Response B_IDLE If ID\ Interrupt. Go to A_IDLE A Type A cable has been plugged in and the device should now respond as a Type A device. If B_SESS_VLD Interrupt. Go to B_PERIPHERAL The A device has turned on VBUS and begins a session.
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On-The-Go Operation K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 924 Freescale Semiconductor, Inc.
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Chapter 41 USB Device Charger Detection Module (USBDCD) 41.1 Preface 41.1.1 References The following publications are referenced in this document. For updates to these specifications, see http://www.usb.org. • USB Battery Charging Specification Revision 1.1, USB Implementers Forum • Universal Serial Bus Specification Revision 2.0, USB Implementers Forum 41.1.2 Acronyms and abbreviations The following table contains acronyms and abbreviations used in this document. Table 41-1.
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Introduction Table 41-1. Acronyms and abbreviated terms (continued) Term Meaning OTG On-The-Go RDM_DWN D– pulldown resistance for data pin contact detect VDAT_REF Data detect reference voltage for the voltage comparator VDP_SRC Voltage source for the D+ line VLGC Threshold voltage for logic high 41.1.3 Glossary The following table shows a glossary of terms used in this document. Table 41-2.
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Chapter 41 USB Device Charger Detection Module (USBDCD) clk reset Digital Block Bus interface & registers Analog Block Timer Unit Voltage Comparator bus Control and Feedback state of D– Current Sink D+ D D– state of D+ Analog Control Unit D– pulldown enable Current Source Voltage Source Figure 41-1. Block diagram The USBDCD module consists of two main blocks: • A digital block provides the programming interface (memory-mapped registers) and includes the timer unit and the analog control unit.
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Module signal descriptions Table 41-3. Module modes and their conditions Module mode Description Conditions when used Enabled The module performs the charger detection sequence. System software should enable the module only when all of the following conditions are true: • The system uses a rechargeable battery. • The device is being used in an FS USB device application. • The device has detected that it is attached to the USB cable.
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Chapter 41 USB Device Charger Detection Module (USBDCD) Table 41-5. Signal descriptions Signal Description I/O usb_dm USB D– analog data signal. The analog block interfaces directly to the D– signal on the USB bus. I/O usb_dp USB D+ analog data signal. The analog block interfaces directly to the D+ signal on the USB bus. I/O avdd331 3.3 V regulated analog supply I avss Analog ground I dvss Digital ground I dvdd 1.2 V digital supply I 1. Voltage must be 3.
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Memory map/Register definition USBDCD memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4003_5014 TIMER1 register (USBDCD_TIMER1) 32 R/W 000A_0028h 41.4.5/ 935 4003_5018 TIMER2 register (USBDCD_TIMER2) 32 R/W 0028_0001h 41.4.6/ 936 26 25 24 0 START 0 16 41.4.1 Control register (USBDCD_CONTROL) Contains the control and interrupt bit fields.
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Chapter 41 USB Device Charger Detection Module (USBDCD) USBDCD_CONTROL field descriptions (continued) Field Description 0 1 23–17 Reserved 16 IE This read-only field is reserved and always has the value zero. Interrupt Enable Enables/disables interrupts to the system. 0 1 15–9 Reserved 8 IF 0 IACK Disable interrupts to the system. Enable interrupts to the system. This field is reserved. Interrupt Flag Determines whether an interrupt is pending. 0 1 7–1 Reserved Do not start the sequence.
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Memory map/Register definition 41.4.
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Chapter 41 USB Device Charger Detection Module (USBDCD) 41.4.3 Status register (USBDCD_STATUS) Provides the current state of the module for system software monitoring.
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Memory map/Register definition USBDCD_STATUS field descriptions (continued) Field Description 19–18 SEQ_STAT Charger Detection Sequence Status Indicates the status of the charger detection sequence. 00 01 10 11 17–16 SEQ_RES The module is either not enabled, or the module is enabled but the data pins have not yet been detected. Data pin contact detection is complete. Charging port detection is complete. Charger type detection is complete.
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Chapter 41 USB Device Charger Detection Module (USBDCD) USBDCD_TIMER0 field descriptions Field Description 31–26 Reserved This read-only field is reserved and always has the value zero. 25–16 TSEQ_INIT Sequence Initiation Time TSEQ_INIT represents the system latency (in ms) measured from the time VBUS goes active to the time system software initiates the charger detection sequence in the USBDCD module.
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Memory map/Register definition USBDCD_TIMER1 field descriptions (continued) Field Description 15–10 Reserved This read-only field is reserved and always has the value zero. 9–0 TVDPSRC_ON Time Period Comparator Enabled This timing parameter is used after detection of the data pin. See "Charging Port Detection". Valid values are 1–1023, but the USB Battery Charging Specification requires a minimum value of 40 ms. 41.4.6 TIMER2 register (USBDCD_TIMER2) TIMER2 contains timing parameters.
PAGE 937
Chapter 41 USB Device Charger Detection Module (USBDCD) 41.5 Functional description The sequence of detecting the presence of charging port and type of charging port involves several hardware components, coordinated by system software. This collection of interacting hardware and software is called the USB Battery Charging Subsystem. The following figure shows the USBDCD module as a component of the subsystem. The following table describes the components.
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Functional description Table 41-13. USB battery charger subsystem components (continued) Component USB Transceiver Description The USB transceiver contains the pullup resistor for the USB D+ signal and the pulldown resistors for the USB D+ and D– signals. The D+ pullup and the D– pulldown are both used during the charger detection sequence. The USB transceiver also outputs the digital state of the D+ and D– signals from the USB bus.
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Chapter 41 USB Device Charger Detection Module (USBDCD) 1 2 Initial VBUS Conditions Detect Charger Detection Phase 3 4 5 6 Data Pin Contact Detection Charging Port Detection Charger Type Detection Timeout T UNIT_CON_ELAPSED = T SEQ_INIT T UNIT_CON_ELAPSED =1s V B U S a t p o rta b le U S B d e v ice I DEV_DCHG D e d ic a te d C h a rg e r C h a rg in g H o s t T SEQ_INIT Dedicated Charger C h a rg in g H o s t I DEV_HCHG_LFS I SUSP 0m A I DP_SRC R DM_DWN FullSpeed Portable USB Device D+
PAGE 940
Functional description Table 41-14. Overview of the charger detection sequence Phase Overview description Full description 1 Initial Conditions Initial system conditions that need to be met before the detection sequence is initiated. Initial System Conditions 2 VBUS Detection System software detects contact of the VBUS signal with the system interrupt pin VBUS_detect.
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Chapter 41 USB Device Charger Detection Module (USBDCD) • Recently plugged into a USB port. • Drawing not more than 2.5 mA total system current from the USB bus. Examples of allowable precursors to this set of initial conditions include: • A powered-down device is subsequently powered-up upon being plugged into the USB bus. • A device in a low power mode subsequently enters run mode upon being plugged into the USB bus. 41.5.1.
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Functional description As a result, when a portable USB device is attached to an upstream port, the portable USB device detects VBUS before the data pins have made contact. The time between power pins and data pins making contact depends on how fast the plug is inserted into the receptable. Delays of several hundred milliseconds are possible. 41.5.1.3.
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Chapter 41 USB Device Charger Detection Module (USBDCD) 41.5.1.4 Charging port detection After it detects that the data pins have made contact, the module waits for a fixed delay of 1 ms, and then attempts to detect whether it is plugged into a charging port.
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Functional description 1. Read the STATUS register. 2. Set CONTROL[IACK] to acknowledge the interrupt. 3. Set CONTROL[SR] to issue a software reset to the module. 4. Disable the module. 5. Communicate the appropriate charge rate to the external battery charger IC; see Table 41-13. 41.5.1.4.
PAGE 945
Chapter 41 USB Device Charger Detection Module (USBDCD) At this point, control has been passed to system software via the interrupt. The rest of the sequence (detecting the type of charging port) is not applicable, so software should: 1. Read the STATUS register. 2. Set CONTROL[IACK] to acknowledge the interrupt. 3. Set CONTROL[SR] to issue a software reset to the module. 4. Disable the module. 41.5.1.
PAGE 946
Functional description 2. Disable the USB controller to prevent transitions on the USB D+ or D– lines from causing spurious interrupt or wakeup events to the system. 3. Set CONTROL[IACK] to acknowledge the interrupt. 4. Set CONTROL[SR] to issue a software reset to the module. 5. Disable the module. 6. Communicate the appropriate charge rate to the external battery charger IC; see Table 41-13. 41.5.1.5.
PAGE 947
Chapter 41 USB Device Charger Detection Module (USBDCD) • Updates the STATUS register to reflect that a timeout error has occured. See Table 41-18 for field values. • Sets the CONTROL[IF] bit. • Generates an interrupt if enabled in CONTROL[IE]. • The detection sequence continues until explicitly halted by software setting the CONTROL[SR] bit. • The Unit Connection Timer continues counting. See the description of the TIMER0 Register.
PAGE 948
Functional description 41.5.2 Interrupts and events The USBDCD module has an interrupt to alert system software of certain events, which are listed in the following table. All events except the Phase Complete event for the Data Pin Detection phase can trigger an interrupt. Table 41-18. Events triggering an interrupt by sequence phase Sequence phase Event Event description STATUS fields1 Data Pin Detection Phase Complete The module has detected data pin contact.
PAGE 949
Chapter 41 USB Device Charger Detection Module (USBDCD) Writes to CONTROL[IF] are ignored. To reset CONTROL[IF], set CONTROL[IACK] to acknowledge the interrupt. Writing to CONTROL[IACK] when CONTROL[IF] is cleared has no effect. 41.5.3 Resets There are two ways to reset various register contents in this module: hardware resets and a software reset. 41.5.3.1 Hardware resets Hardware resets originate at the system or device level and propagate down to the individual module level.
PAGE 950
Initialization information Note Software must always initiate a software reset before starting the sequence to ensure the module is in a known state. 41.6 Initialization information This module has been designed for minimal configuration while retaining significant programmability. The CLOCK register needs to be initialized to the actual system clock frequency, unless the default value already matches the system requirements.
PAGE 951
Chapter 41 USB Device Charger Detection Module (USBDCD) The module is also compatible with systems that do check the strength of the battery. In these systems, if it is known that the battery is weak or dead, software can delay connecting to the USB while charging at 1.5A. Once the battery is charged to the good battery threshold, software can then connect to the USB host by pulling the D+ line high. 41.7.
PAGE 952
Application information K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 952 Freescale Semiconductor, Inc.
PAGE 953
Chapter 42 USB Voltage Regulator 42.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The USB Voltage Regulator module is a LDO linear voltage regulator to provide 3.3V power from an input power supply varying from 2.7 V to 5.5 V. It consists of one 3.3 V power channel. When the input power supply is below 3.6 V, the regulator goes to passthrough mode.
PAGE 954
Introduction 42.1.1 Overview A simplified block diagram for the USB Voltage Regulator module is shown below. STANDBY Regulator Yes No Other Modules STANDBY Power Supply reg33_in Regulated Output Voltage reg33_out RUN Regulator ESR: 5m -> 100m Ohms Voltage Regulator External Capacitor typical = 2.2uF Chip Figure 42-2. USB Voltage Regulator Block Diagram This module uses 2 regulators in parallel.
PAGE 955
Chapter 42 USB Voltage Regulator • Automatic current limiting if the load current is greater than 290 mA. • Automatic power-up once some voltage is applied to the regulator input. • Pass-through mode for regulator input voltages less than 3.6 V • Small output capacitor: 2.2 uF • Stable with aluminum, tantalum or ceramic capacitors. 42.1.
PAGE 956
USB Voltage Regulator Module Signal Descriptions K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 956 Freescale Semiconductor, Inc.
PAGE 957
Chapter 43 SPI (DSPI) 43.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The serial peripheral interface (SPI) module provides a synchronous serial bus for communication between an MCU and an external peripheral device. 43.1.1 Block Diagram The block diagram of this module is as follows: K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 Freescale Semiconductor, Inc.
PAGE 958
Introduction INTC eDMA Slave Bus Interface Clock/Reset SPI DMA and Interrupt Control POPR TX FIFO RX FIFO PUSHR CMD Data Data 32 32 SOUT Shift Register SIN SCK S PI Baud Rate, Delay & Transfer Control PCS[x]/SS 8 Figure 43-1. DSPI Block Diagram 43.1.
PAGE 959
Chapter 43 SPI (DSPI) • Programmable transfer attributes on a per-frame basis: • 2 transfer attribute registers • Serial clock (SCK) with programmable polarity and phase • Various programmable delays • Programmable serial frame size of 4–16 bits, expandable by software control • SPI frames longer than 16 bits can be supported using the continuous selection format • Continuously held chip select capability • 5 peripheral chip selects (PCSs), expandable to 32 with external demultiplexer • Deglitching support
PAGE 960
Introduction 43.1.3 DSPI Configurations The DSPI module always operates in SPI configuration. 43.1.3.1 SPI Configuration The SPI configuration allows the DSPI to send and receive serial data. This configuration allows the DSPI to operate as a basic SPI block with internal FIFOs supporting external queue operation. Transmitted data and received data reside in separate FIFOs. The host CPU or a DMA controller read the received data from the Receive FIFO and write transmit data to the Transmit FIFO.
PAGE 961
Chapter 43 SPI (DSPI) • Slave mode • Module Disable mode • MCU-specific modes: • External Stop mode • Debug mode The DSPI enters module-specific modes when the host writes a DSPI register. The MCUspecific modes are controlled by signals external to the DSPI. The MCU-specific modes are modes that an MCU may enter in parallel to the DSPI block-specific modes. 43.1.4.1 Master Mode Master mode allows the DSPI to initiate and control serial communication.
PAGE 962
DSPI signal descriptions 43.1.4.5 Debug Mode Debug mode is used for system development and debugging. The MCR[FRZ] bit controls DSPI behavior in the Debug mode: • If the bit is set, the DSPI stops all serial transfers, when the MCU is in debug mode. • If the bit is cleared, the MCU debug mode has no effect on the DSPI. 43.2 DSPI signal descriptions This section provides description of the DSPI signals. The following table lists the signals that may connect off chip depending on device implementation.
PAGE 963
Chapter 43 SPI (DSPI) 43.2.2 PCS1 – PCS3 — Peripheral Chip Selects 1 – 3 PCS1 – PCS3 are output signals in Master mode. In Slave mode, these signals are unused. 43.2.3 PCS4 — Peripheral Chip Select 4 In Master mode, PCS4 is an output signal. In Slave mode, this signal is unused. 43.2.4 SIN — Serial Input SIN is a serial data input signal. 43.2.5 SOUT — Serial Output SOUT is a serial data output signal. 43.2.6 SCK — Serial Clock SCK is a serial communication clock signal.
PAGE 964
Memory Map/Register Definition SPI memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_C008 DSPI Transfer Count Register (SPI0_TCR) 32 R/W 0000_0000h 43.3.2/ 968 4002_C00C DSPI Clock and Transfer Attributes Register (In Master Mode) (SPI0_CTAR0) 32 R/W 7800_0000h 43.3.3/ 968 4002_C00C DSPI Clock and Transfer Attributes Register (In Slave Mode) (SPI0_CTAR0_SLAVE) 32 R/W 7800_0000h 43.3.
PAGE 965
Chapter 43 SPI (DSPI) 43.3.1 DSPI Module Configuration Register (SPIx_MCR) Contains bits to configure various attributes associated with DSPI operations. The HALT and MDIS bits can be changed at any time, but the effect takes place only on the next frame boundary. Only the HALT and MDIS bits in the MCR can be changed, while the DSPI is in the Running state.
PAGE 966
Memory Map/Register Definition SPIx_MCR field descriptions (continued) Field Description 10 11 27 FRZ Freeze Enables the DSPI transfers to be stopped on the next frame boundary when the device enters Debug mode. 0 1 26 MTFE 24 ROOE Enables a modified transfer format to be used. 20–16 PCSIS[4:0] Receive FIFO Overflow Overwrite Enable In the RX FIFO overflow condition, configures the DSPI to ignore the incoming serial data or overwrite existing data.
PAGE 967
Chapter 43 SPI (DSPI) SPIx_MCR field descriptions (continued) Field Description When the TX FIFO is disabled, the transmit part of the DSPI operates as a simplified double-buffered SPI. This bit can be written only when the MDIS bit is cleared. 0 1 12 DIS_RXF Disable Receive FIFO When the RX FIFO is disabled, the receive part of the DSPI operates as a simplified double-buffered SPI. This bit can only be written when the MDIS bit is cleared. 0 1 11 CLR_TXF Flushes the TX FIFO.
PAGE 968
Memory Map/Register Definition 43.3.2 DSPI Transfer Count Register (SPIx_TCR) TCR contains a counter that indicates the number of SPI transfers made. The transfer counter is intended to assist in queue management. Do not write the TCR when the DSPI is in the Running state.
PAGE 969
Chapter 43 SPI (DSPI) Addresses: SPI0_CTAR0 is 4002_C000h base + Ch offset = 4002_C00Ch SPI0_CTAR1 is 4002_C000h base + 10h offset = 4002_C010h Bit 31 30 29 28 27 23 22 PCSSCK 21 20 19 18 17 16 LSBFE 24 CPHA 25 CPOL R 26 Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 DBR W R FMSZ CSSCK W Reset 0 0 ASC 0 0 0 0 PASC PDT PBR DT 0 0 0 0 BR 0 0 0 0 SPIx_CTARn field descriptions Field 31 DBR De
PAGE 970
Memory Map/Register Definition SPIx_CTARn field descriptions (continued) Field Description can cause errors in the transfer due to the peripheral device interpreting the switch of clock polarity as a valid clock edge. 0 1 25 CPHA Clock Phase Selects which edge of SCK causes data to change and which edge causes data to be captured. This bit is used in both Master and Slave mode. For successful communication between serial devices, the devices must have identical clock phase settings.
PAGE 971
Chapter 43 SPI (DSPI) SPIx_CTARn field descriptions (continued) Field 17–16 PBR Description Baud Rate Prescaler Selects the prescaler value for the baud rate. This field is used only in Master mode. The baud rate is the frequency of the SCK. The system clock is divided by the prescaler value before the baud rate selection takes place. See the BR field description for details on how to compute the baud rate. 00 01 10 11 15–12 CSSCK Baud Rate Prescaler value is 2. Baud Rate Prescaler value is 3.
PAGE 972
Memory Map/Register Definition SPIx_CTARn field descriptions (continued) Field Description Selects the scaler value for the After SCK Delay. This field is used only in Master mode. The After SCK Delay is the delay between the last edge of SCK and the negation of PCS. The delay is a multiple of the system clock period, and it is computed according to the following equation: tASC = (1/fSYS) x PASC x ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for scaler values.
PAGE 973
Chapter 43 SPI (DSPI) SPIx_CTARn field descriptions (continued) Field Description Table 43-34. DSPI baud rate scaler (continued) CTARn[BR] Baud rate scaler value 1111 32768 43.3.4 DSPI Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTAR_SLAVE) When the DSPI is configured as an SPI bus slave, the CTAR0 register is used.
PAGE 974
Memory Map/Register Definition SPIx_CTARn_SLAVE field descriptions (continued) Field Description 22 Reserved This read-only field is reserved and always has the value zero. 21–0 Reserved This read-only field is reserved and always has the value zero. 43.3.5 DSPI Status Register (SPIx_SR) SR contains status and flag bits. The bits reflect the status of the DSPI and indicate the occurrence of events that can generate interrupt or DMA requests.
PAGE 975
Chapter 43 SPI (DSPI) SPIx_SR field descriptions (continued) Field Description 0 1 30 TXRXS TX and RX Status Reflects the run status of the DSPI. 0 1 29 Reserved 28 EOQF End of Queue Flag Indicates that the last entry in a queue has been transmitted when the DSPI is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit set in the command halfword and the end of the transfer is reached. The EOQF bit remains set until cleared by writing a 1 to it.
PAGE 976
Memory Map/Register Definition SPIx_SR field descriptions (continued) Field 19 RFOF Description Receive FIFO Overflow Flag Indicates an overflow condition in the RX FIFO. The field is set when the RX FIFO and shift register are full and a transfer is initiated. The bit remains set until it is cleared by writing a 1 to it. 0 1 18 Reserved 17 RFDF This read-only field is reserved and always has the value zero.
PAGE 977
Chapter 43 SPI (DSPI) 43.3.6 DSPI DMA/Interrupt Request Select and Enable Register (SPIx_RSER) RSER controls DMA and interrupt requests. Do not write to the RSER while the DSPI is in the Running state.
PAGE 978
Memory Map/Register Definition SPIx_RSER field descriptions (continued) Field 25 TFFF_RE Description Transmit FIFO Fill Request Enable Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit selects between generating an interrupt request or a DMA request. 0 1 24 TFFF_DIRS TFFF interrupts or DMA requests are disabled. TFFF interrupts or DMA requests are enabled. Transmit FIFO Fill DMA or Interrupt Request Select Selects between generating a DMA request or an interrupt request.
PAGE 979
Chapter 43 SPI (DSPI) SPIx_RSER field descriptions (continued) Field Description 14 Reserved This read-only field is reserved and always has the value zero. 13–0 Reserved This read-only field is reserved and always has the value zero. 43.3.7 DSPI PUSH TX FIFO Register In Master Mode (SPIx_PUSHR) PUSHR provides the means to write to the TX FIFO. Data written to this register is transferred to the TX FIFO .
PAGE 980
Memory Map/Register Definition SPIx_PUSHR field descriptions (continued) Field Description Selects which CTAR to use in master mode to specify the transfer attributes for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chapter on chip configuration to determine how many CTARs this device has. You should not program a value in this field for a register that is not present.
PAGE 981
Chapter 43 SPI (DSPI) 43.3.8 DSPI PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE) PUSHR provides the means to write to the TX FIFO. Data written to this register is transferred to the TX FIFO. Eight- or sixteen-bit write accesses to the Data Field of PUSHR transfers the 16 bit Data Field of PUSHR to the TX FIFO. The register structure is different in master and slave modes. The register structure is different in master and slave modes.
PAGE 982
Memory Map/Register Definition SPIx_POPR field descriptions Field Description 31–0 RXDATA Received Data Contains the SPI data from the RX FIFO entry to which the Pop Next Data Pointer points. 43.3.10 DSPI Transmit FIFO Registers (SPIx_TXFRn) TXFRn registers provide visibility into the TX FIFO for debugging purposes. Each register is an entry in the TX FIFO. The registers are read-only and cannot be modified. Reading the TXFRx registers does not alter the state of the TX FIFO.
PAGE 983
Chapter 43 SPI (DSPI) 43.3.11 DSPI Receive FIFO Registers (SPIx_RXFRn) RXFRn provide visibility into the RX FIFO for debugging purposes. Each register is an entry in the RX FIFO. The RXFRs are read-only. Reading the RXFRx registers does not alter the state of the RX FIFO.
PAGE 984
Functional description See ../dil/DSPI_BG_V5x.xml#CTAR_MASTER_2 for information on the fields of CTAR registers. Typical master to slave connections are shown in the following figure. When a data transfer operation is performed, data is serially shifted a predetermined number of bit positions. Because the modules are linked, data is exchanged between the master and the slave. The data that was in the master shift register is now in the shift register of the slave, and vice versa.
PAGE 985
Chapter 43 SPI (DSPI) • SR[EOQF] bit is clear • MCU is not in the Debug mode or the MCR[FRZ] bit is clear • MCR[HALT] bit is clear The DSPI stops or transitions from Running to Stopped after the current frame when any one of the following conditions exist: • SR[EOQF] bit is set • MCU in the Debug mode and the MCR[FRZ] bit is set • MCR[HALT] bit is set State transitions from Running to Stopped occur on the next frame boundary if a transfer is in progress, or immediately if no transfers are in progress. 43.
PAGE 986
Functional description various bits that help with queue management and transfer protocol . See ../dil/ DSPI_BG_V5x.xml#PUSHR_MASTER for details on the SPI command fields. The data in the executing TX FIFO entry is loaded into the shift register and shifted out on the Serial Out (SOUT) pin. In SPI Master mode, each SPI frame to be transmitted has a command associated with it, allowing for transfer attribute control on a frame by frame basis. 43.4.2.
PAGE 987
Chapter 43 SPI (DSPI) The TX FIFO Counter field (TXCTR) in the DSPI Status Register (SR) indicates the number of valid entries in the TX FIFO. The TXCTR is updated every time a 8- or 16-bit write takes place to the Data Field of DSPI_PUSHR or SPI data is transferred into the shift register from the TX FIFO. The TXNXTPTR field indicates the TX FIFO Entry that will be transmitted during the next transfer.
PAGE 988
Functional description shift register is transferred into the RX FIFO. SPI data are removed (popped) from the RX FIFO by reading the DSPI POP RX FIFO Register (POPR). RX FIFO entries can only be removed from the RX FIFO by reading the POPR or by flushing the RX FIFO. The RX FIFO Counter field (RXCTR) in the DSPI Status Register (SR) indicates the number of valid entries in the RX FIFO. The RXCTR is updated every time the POPR is read or SPI data is copied from the shift register to the RX FIFO.
PAGE 989
Chapter 43 SPI (DSPI) 43.4.3 DSPI baud rate and clock delay generation The SCK frequency and the delay values for serial transfer are generated by dividing the system clock frequency by a prescaler and a scaler with the option for doubling the baud rate. The following figure shows conceptually how the SCK signal is generated. System Clock 1 Prescaler SCK 1+DBR Scaler Figure 43-48. Communications clock prescalers and scalers 43.4.3.1 Baud rate generator The baud rate is the frequency of the SCK.
PAGE 990
Functional description NOTE The clock frequency mentioned in the preceding table is given as an example. Refer to the clocking chapter for the frequency used to drive this module in the device. 43.4.3.3 After SCK Delay (tASC) The After SCK Delay is the length of time between the last edge of SCK and the negation of PCS. See Figure 43-49 and Figure 43-50 for illustrations of the After SCK delay.
PAGE 991
Chapter 43 SPI (DSPI) When in Non-Continuous Clock mode the tDT delay is configured according to the equation specified in the CTAR[DT] bitfield description. When in Continuous Clock mode, the delay is fixed at 1 SCK period. 43.4.4 Transfer formats The SPI serial communication is controlled by the Serial Communications Clock (SCK) signal and the PCS signals. The SCK signal provided by the master device synchronizes shifting and sampling of the data on the SIN and SOUT pins.
PAGE 992
Functional description 43.4.4.1 Classic SPI Transfer Format (CPHA = 0) The transfer format shown in following figure is used to communicate with peripheral SPI slave devices where the first data bit is available on the first clock edge. In this format, the master and slave sample their SIN pins on the odd-numbered SCK edges and change the data on their SOUT pins on the even-numbered SCK edges.
PAGE 993
Chapter 43 SPI (DSPI) 43.4.4.2 Classic SPI Transfer Format (CPHA = 1) This transfer format shown in the following figure is used to communicate with peripheral SPI slave devices that require the first SCK edge before the first data bit becomes available on the slave SOUT pin.
PAGE 994
Functional description 43.4.4.3 Continuous Selection Format Some peripherals must be deselected between every transfer. Other peripherals must remain selected between several sequential serial transfers. The Continuous Selection Format provides the flexibility to handle the following case. The Continuous Selection Format is enabled for the SPI configuration by setting the CONT bit in the SPI command.
PAGE 995
Chapter 43 SPI (DSPI) SCK (CPOL = 0) SCK (CPOL = 1) Master SOUT Master SIN PCS tCSC t tCSC = PC S to SCK del ay t ASC t ASC CSC = After SCK delay Figure 43-52. Example of continuous transfer (CPHA=1, CONT=1) When using DSPI with continuous selection follow these rules: • All transmit commands must have the same PCSn bits programming. • The CTARs, selected by transmit commands, must be programmed with the same transfer attributes. Only FMSZ field can be programmed differently in these CTARs.
PAGE 996
Functional description 43.4.5 Continuous Serial Communications Clock The DSPI provides the option of generating a Continuous SCK signal for slave peripherals that require a continuous clock. Continuous SCK is enabled by setting the CONT_SCKE bit in the MCR. Enabling this bit generates the Continuous SCK regardless of the MCR[HALT] bit status. Continuous SCK is valid in all configurations. Continuous SCK is only supported for CPHA=1. Clearing CPHA is ignored if the CONT_SCKE bit is set.
PAGE 997
Chapter 43 SPI (DSPI) SCK (CPOL = 0) SCK (CPOL = 1) Master SOUT Master SIN PCS tDT Figure 43-53. Continuous SCK Timing Diagram (CONT=0) If the CONT bit in the TX FIFO entry is set, PCS remains asserted between the transfers. Under certain conditions, SCK can continue with PCS asserted, but with no data being shifted out of SOUT, that is, SOUT pulled high. This can cause the slave to receive incorrect data. Those conditions include: • Continuous SCK with CONT bit set, but no data in the TX FIFO.
PAGE 998
Functional description 43.4.6 Slave Mode Operation Constraints Slave mode logic shift register is buffered. This allows data streaming operation, when the DSPI is permanently selected and data is shifted in with a constant rate. The transmit data is transferred at second SCK clock edge of the each frame to the shift register if the SS signal is asserted and any time when transmit data is ready and SS signal is negated.
PAGE 999
Chapter 43 SPI (DSPI) 43.4.7.1 End of Queue Interrupt Request The End of Queue Request indicates that the end of a transmit queue is reached. The End of Queue Request is generated when the EOQ bit in the executing SPI command is set and the EOQF_RE bit in the RSER is set. NOTE This interrupt request is generated when the last bit of the SPI frame with EOQ bit set is transmitted. 43.4.7.2 Transmit FIFO Fill Interrupt or DMA Request The Transmit FIFO Fill Request indicates that the TX FIFO is not full.
PAGE 1000
Functional description 43.4.7.4 Transmit FIFO Underflow Interrupt Request The Transmit FIFO Underflow Request indicates that an underflow condition in the TX FIFO has occurred. The transmit underflow condition is detected only for the DSPI, operating in Slave mode and SPI configuration . The TFUF bit is set when the TX FIFO of a DSPI is empty, and a transfer is initiated from an external SPI master. If the TFUF bit is set while the TFUF_RE bit in the RSER is set, an interrupt request is generated. 43.4.7.
PAGE 1001
Chapter 43 SPI (DSPI) 43.4.8.1 Stop mode (External Stop mode) The DSPI supports the Stop mode protocol. When a request is made to enter External Stop mode, the DSPI block acknowledges the request . If a serial transfer is in progress, the DSPI waits until it reaches the frame boundary before it is ready to have its clocks shut off . While the clocks are shut off, the DSPI memory-mapped logic is not accessible. This also puts the DSPI in STOPPED state. The SR[TXRXS] bit is cleared to indicate STOPPED state.
PAGE 1002
Initialization/application information 43.5.1 How to manage DSPI queues The queues are not part of the DSPI, but the DSPI includes features in support of queue management. Queues are primarily supported in SPI configuration. 1. When DSPI executes last command word from a queue, the EOQ bit in the command word is set to indicate to the DSPI that this is the last entry in the queue. 2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ flag (EOQF) in the SR is set.
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Chapter 43 SPI (DSPI) 2. Clear the transmit and receive FIFOs by writing a 1 to the CLR_TXF and CLR_RXF bits in MCR. 3. Set the appropriate mode in MCR[MSTR] and enable the DSPI by clearing MCR[HALT]. 43.5.3 Initializing DSPI in Master/Slave Modes Once the appropriate mode in MCR[MSTR] is configured, the DSPI is enabled by clearing MCR[HALT]. It should be ensured that DSPI Slave is enabled before enabling DSPI Master.
PAGE 1004
Initialization/application information Table 43-59. Baud rate values (bps) Baud Rate Scaler Values Baud rate divider prescaler values 2 3 5 7 2 25.0M 16.7M 10.0M 7.14M 4 12.5M 8.33M 5.00M 3.57M 6 8.33M 5.56M 3.33M 2.38M 8 6.25M 4.17M 2.50M 1.79M 16 3.12M 2.08M 1.25M 893k 32 1.56M 1.04M 625k 446k 64 781k 521k 312k 223k 128 391k 260k 156k 112k 256 195k 130k 78.1k 55.8k 512 97.7k 65.1k 39.1k 27.9k 1024 48.8k 32.6k 19.5k 14.0k 2048 24.4k 16.3k 9.
PAGE 1005
Chapter 43 SPI (DSPI) Table 43-60. Delay values Delay scaler values Delay prescaler values 1 3 5 7 2 20.0 ns 60.0 ns 100.0 ns 140.0 ns 4 40.0 ns 120.0 ns 200.0 ns 280.0 ns 8 80.0 ns 240.0 ns 400.0 ns 560.0 ns 16 160.0 ns 480.0 ns 800.0 ns 1.1 μs 32 320.0 ns 960.0 ns 1.6 μs 2.2 μs 64 640.0 ns 1.9 μs 3.2 μs 4.5 μs 128 1.3 μs 3.8 μs 6.4 μs 9.0 μs 256 2.6 μs 7.7 μs 12.8 μs 17.9 μs 512 5.1 μs 15.4 μs 25.6 μs 35.8 μs 1024 10.2 μs 30.7 μs 51.2 μs 71.
PAGE 1006
Initialization/application information Push TX FIFO Register TX FIFO Base Transmit Next Data Pointer Entry A (first in) Entry B Entry C Entry D (last in) - Shift Register +1 TX FIFO Counter SOUT -1 Figure 43-55. TX FIFO pointers and counter 43.5.6.
PAGE 1007
Chapter 43 SPI (DSPI) The memory address of the last-in entry in the RX FIFO is computed by the following equation: RX FIFO Base - Base address of RX FIFO RXCTR - RX FIFO counter POPNXTPTR - Pop Next Pointer RX FIFO Depth - Receive FIFO depth, implementation specific K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 Freescale Semiconductor, Inc.
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Initialization/application information K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 1008 Freescale Semiconductor, Inc.
PAGE 1009
Chapter 44 Inter-Integrated Circuit (I2C) 44.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The inter-integrated circuit (I2C, I2C, or IIC) module provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbit/s with maximum bus loading and timing. The I2C device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading.
PAGE 1010
Introduction • • • • • • 10-bit address extension Support for System Management Bus (SMBus) Specification, version 2 Programmable glitch input filter Low power mode wakeup on slave address match Range slave address support DMA support 44.1.2 Modes of operation The I2C module's operation in various low power modes is as follows: • Run mode: This is the basic mode of operation. To conserve power in this mode, disable the module.
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Chapter 44 Inter-Integrated Circuit (I2C) Address Module Enable Write/Read Interrupt ADDR_DECODE DATA_MUX CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync START STOP Arbitration Control Clock Control In/Out Data Shift Register Address Compare SDA SCL Figure 44-1. I2C Functional block diagram 44.2 I2C signal descriptions The signal properties of I2C are shown in the following table. Table 44-1.
PAGE 1012
Memory map and register descriptions I2C memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4006_6000 I2C Address Register 1 (I2C0_A1) 8 R/W 00h 44.3.1/ 1012 4006_6001 I2C Frequency Divider register (I2C0_F) 8 R/W 00h 44.3.2/ 1013 4006_6002 I2C Control Register 1 (I2C0_C1) 8 R/W 00h 44.3.3/ 1014 4006_6003 I2C Status register (I2C0_S) 8 R/W 80h 44.3.4/ 1016 4006_6004 I2C Data I/O register (I2C0_D) 8 R/W 00h 44.3.
PAGE 1013
Chapter 44 Inter-Integrated Circuit (I2C) I2Cx_A1 field descriptions (continued) Field 0 Reserved Description This read-only field is reserved and always has the value zero. 44.3.2 I2C Frequency Divider register (I2Cx_F) Addresses: I2C0_F is 4006_6000h base + 1h offset = 4006_6001h Bit Read Write Reset 7 6 5 4 3 MULT 0 2 1 0 0 0 0 ICR 0 0 0 0 I2Cx_F field descriptions Field 7–6 MULT Description The MULT bits define the multiplier factor mul.
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Memory map and register descriptions I2Cx_F field descriptions (continued) Field Description MULT ICR 2h Hold times (μs) SDA SCL Start SCL Stop 00h 3.500 3.000 5.500 1h 07h 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h 1.125 4.750 5.125 44.3.
PAGE 1015
Chapter 44 Inter-Integrated Circuit (I2C) I2Cx_C1 field descriptions (continued) Field Description Selects the direction of master and slave transfers. In master mode this bit must be set according to the type of transfer required. Therefore, for address cycles, this bit is always set. When addressed as a slave this bit must be set by software according to the SRW bit in the status register.
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Memory map and register descriptions 44.3.4 I2C Status register (I2Cx_S) Addresses: I2C0_S is 4006_6000h base + 3h offset = 4006_6003h Bit Read Write Reset 7 6 TCF IAAS 1 5 4 BUSY ARBL w1c 0 0 0 3 RAM 0 2 1 0 SRW IICIF w1c 0 RXAK 0 0 I2Cx_S field descriptions Field 7 TCF Description Transfer Complete Flag This bit sets on the completion of a byte and acknowledge bit transfer. This bit is valid only during or immediately following a transfer to or from the I2C module.
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Chapter 44 Inter-Integrated Circuit (I2C) I2Cx_S field descriptions (continued) Field Description This bit is set by any of the following conditions: • Any nonzero calling address is received that matches the address in the RA register. • The RMEN bit is set and the calling address is within the range of values of the A1 and RA registers. Writing the C1 register with any value clears this bit.
PAGE 1018
Memory map and register descriptions I2Cx_D field descriptions (continued) Field Description In master transmit mode, when data is written to this register, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data. NOTE: When making the transition out of master receive mode, switch the I2C mode before reading the Data register to prevent an inadvertent initiation of a master receive data transfer.
PAGE 1019
Chapter 44 Inter-Integrated Circuit (I2C) I2Cx_C2 field descriptions (continued) Field 4 SBRC Description Slave Baud Rate Control Enables independent slave mode baud rate at maximum frequency, which forces clock stretching on SCL in very fast I2C modes. To a slave, an example of a "very fast" mode is when the master transfers at 40 kbps but the slave can capture the master's data at only 10 kbps.
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Memory map and register descriptions 44.3.8 I2C Range Address register (I2Cx_RA) Addresses: I2C0_RA is 4006_6000h base + 7h offset = 4006_6007h Bit Read Write Reset 7 6 5 4 3 2 1 RAD 0 0 0 0 0 0 0 0 0 0 I2Cx_RA field descriptions Field 7–1 RAD 0 Reserved Description Range Slave Address This field contains the slave address to be used by the I2C module. The field is used in the 7-bit address scheme. Any nonzero write enables this register.
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Chapter 44 Inter-Integrated Circuit (I2C) I2Cx_SMB field descriptions Field 7 FACK Description Fast NACK/ACK Enable For SMBus packet error checking, the CPU must be able to issue an ACK or NACK according to the result of receiving data byte. 0 1 6 ALERTEN An ACK or NACK is sent on the following receiving data byte Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
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Memory map and register descriptions I2Cx_SMB field descriptions (continued) Field Description 0 1 0 SHTF2IE No SCL high and SDA low timeout occurs SCL high and SDA low timeout occurs SHTF2 Interrupt Enable Enables SCL high and SDA low timeout interrupt. 0 1 SHTF2 interrupt is disabled SHTF2 interrupt is enabled 44.3.
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Chapter 44 Inter-Integrated Circuit (I2C) 44.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL) Addresses: I2C0_SLTL is 4006_6000h base + Bh offset = 4006_600Bh Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 SSLT[7:0] 0 0 0 0 I2Cx_SLTL field descriptions Field 7–0 SSLT[7:0] Description Least significant byte of SCL low timeout value that determines the timeout period of SCL low. 44.4 Functional description This section provides a comprehensive functional description of the I2C module. 44.
PAGE 1024
Functional description M SB SCL SDA 1 SDA Start Signal 3 4 5 6 7 8 9 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 R /W C a llin g A d d re s s Start Signal SCL M SB LSB 2 3 4 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 D a ta B y te 5 6 7 8 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 R /W C a llin g A d d re s s 1 9 R e a d / Ack W rite Bit XX 9 No Stop Ack Signal Bit M SB LSB 2 2 R e a d / Ack W rite Bit M SB 1 XXX LSB 1 LSB 2 3 4 5 6 7 8 9 A D 7 A D 6 A D 5
PAGE 1025
Chapter 44 Inter-Integrated Circuit (I2C) No two slaves in the system can have the same address. If the I2C module is the master, it must not transmit an address that is equal to its own slave address. The I2C module cannot be master and slave at the same time. However, if arbitration is lost during an address cycle, the I2C module reverts to slave mode and operates correctly even if it is being addressed by another master. 44.4.1.
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Functional description 44.4.1.5 Repeated START signal The master may generate a START signal followed by a calling command without generating a STOP signal first. This action is called a repeated START. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 44.4.1.6 Arbitration procedure The I2C bus is a true multimaster bus that allows more than one master to be connected on it.
PAGE 1027
Chapter 44 Inter-Integrated Circuit (I2C) S ta rt C o u n tin g H ig h P e rio d D e la y SCL1 SCL2 SCL In te rn a l C o u n te r R e s e t Figure 44-27. I2C clock synchronization 44.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfers. A slave device may hold SCL low after completing a single byte transfer (9 bits). In this case, it halts the bus clock and forces the master clock into wait states until the slave releases SCL. 44.4.1.
PAGE 1028
Functional description Table 44-28.
PAGE 1029
Chapter 44 Inter-Integrated Circuit (I2C) 44.4.2 10-bit address For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 44.4.2.1 Master-transmitter addresses a slave-receiver The transfer direction is not changed.
PAGE 1030
Functional description After a repeated START condition (Sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressed because R/W = 1 (for 10-bit devices), or the 11110XX slave address (for 7-bit devices) does not match. Table 44-30.
PAGE 1031
Chapter 44 Inter-Integrated Circuit (I2C) provide manufacturer information, tell the system what its model/part number is, save its state for a suspend event, report different types of errors, accept control parameters, and return its status. 44.4.4.1 Timeouts The TTIMEOUT,MIN parameter allows a master or slave to conclude that a defective device is holding the clock low indefinitely or a master is intentionally trying to drive devices off the bus.
PAGE 1032
Functional description When the SMBDAT signal is low and the SMBCLK signal is high for a period of time, another kind of timeout occurs. The time period must be defined in software. SHTF2 is used as the flag when the time limit is reached. This flag is also an interrupt resource, so it triggers IICIF. 44.4.4.1.3 CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT The following figure illustrates the definition of the timeout intervals TLOW:SEXT and TLOW:MEXT.
PAGE 1033
Chapter 44 Inter-Integrated Circuit (I2C) The PEC is a CRC-8 error checking byte, calculated on all the message bytes. The PEC is appended to the message by the device that supplied the last data byte. If the PEC is present but not correct, a NACK is issued by the receiver. Otherwise an ACK is issued. To calculate the CRC-8 by software, this module can hold the SCL line low after receiving the eighth SCL (8th bit) if this byte is a data byte.
PAGE 1034
Functional description Table 44-31. Interrupt summary Interrupt source Status Flag Local enable Complete 1-byte transfer TCF IICIF IICIE Match of received calling address IAAS IICIF IICIE Arbitration lost ARBL IICIF IICIE SMBus SCL low timeout SLTF IICIF IICIE SMBus SCL high SDA low timeout SHTF2 IICIF IICIE & SHTF2IE Wakeup from stop or wait mode IAAS IICIF IICIE & WUEN 44.4.6.
PAGE 1035
Chapter 44 Inter-Integrated Circuit (I2C) Arbitration is lost in the following circumstances: 1. SDA is sampled as low when the master drives high during an address or data transmit cycle. 2. SDA is sampled as low when the master drives high during the acknowledge bit of a data receive cycle. 3. A START cycle is attempted when the bus is busy. 4. A repeated START cycle is requested in slave mode. 5. A STOP condition is detected when the master did not request it.
PAGE 1036
Functional description Noise suppress circuits SCL, SDA internal signals SCL, SDA external signals DFF DFF DFF DFF Figure 44-29. Programmable input glitch filter diagram 44.4.8 Address matching wakeup When a primary, range, or general call address match occurs when the I2C module is in slave receive mode, the MCU wakes from a low power mode with no peripheral bus running. Data sent on the bus that is the same as a target device address might also wake the target MCU.
PAGE 1037
Chapter 44 Inter-Integrated Circuit (I2C) NOTE In 10-bit address mode transmission, the addresses to send occupy 2-3 bytes. During this transfer period, the DMA must be disabled because the C1 register is written to send a repeat start or to change the transfer direction. 44.5 Initialization/application information Module Initialization (Slave) 1. Write: Control Register 2 • to enable or disable general call • to select 10-bit or 7-bit addressing mode 2.
PAGE 1038
Initialization/application information Clear IICIF Y Tx Master mode? N Rx Y Tx/Rx? Last byte transmitted? Y Arbitration lost? N Clear ARBL N N Last byte to be read? RXAK=0? N End of address cycle (master Rx)? Y Y (read) 2nd to last byte to be read? Write next byte to Data reg Set TXACK Address transfer see note 1 N Data transfer see note 2 Tx/Rx? Tx Y Generate stop signal (MST=0) IIAAS=1? Rx SRW=1? N (write) N N Y IIAAS=1? Y N Y Y Y Set TX mode ACK from receiver? N Writ
PAGE 1039
Chapter 44 Inter-Integrated Circuit (I2C) Y N SLTF or SHTF2=1? N FACK=1? See typical I2C interrupt routine flow chart Y Clear IICIF Y Tx Master mode? N Rx Y Tx/Rx? Last byte transmitted? Y Last byte to be read? Y N RXAK=0? 2nd to last byte to be read? N N Y Y (read) N Delay (note 2) Read data and Soft CRC Set TXAK to proper value Delay (note 2) Set TXACK=1 Clear FACK=0 Clear IICIF Write next byte to Data reg Switch to Rx mode Generate stop signal (MST=0) Y IAAS=1? Y Delay (not
PAGE 1040
Initialization/application information K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 1040 Freescale Semiconductor, Inc.
PAGE 1041
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The UART allows asynchronous serial communication with peripheral devices and CPUs. 45.1.1 Features The UART includes the following features: • Full-duplex operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.
PAGE 1042
Introduction • 11-bit break character detection option • Independent FIFO structure for transmit and receive • Two receiver wakeup methods: • Idle line wakeup • Address mark wakeup • Address match feature in the receiver to reduce address mark wakeup ISR overhead • Ability to select MSB or LSB to be first bit on wire • Hardware flow control support for request to send (RTS) and clear to send (CTS) signals • Support for ISO 7816 protocol to interface with SIM cards and smart cards • Support for T=0 and T=1
PAGE 1043
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) • Transmitter data buffer at or below watermark • Transmission complete • Receiver data buffer at or above watermark • Idle receiver input • Receiver data buffer overrun • Receiver data buffer underflow • Transmit data buffer overflow • Noise error • Framing error • Parity error • Active edge on receive pin • LIN break detect • Receiver framing error detection • Hardware parity generation and checking • 1/16 bit-time noise detection • DMA interf
PAGE 1044
UART signal descriptions 45.1.2.2 Wait mode UART operation in the Wait mode depends on the state of the C1[UARTSWAI] field. • If C1[UARTSWAI] is cleared, and the CPU is in Wait mode, the UART operates normally. • If C1[UARTSWAI] is set, and the CPU is in Wait mode, the UART clock generation ceases and the UART module enters a power conservation state. C1[UARTSWAI] does not initiate any power down or power up procedures for the ISO-7816 smartcard interface.
PAGE 1045
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.2.1 Detailed signal descriptions The detailed signal descriptions of the UART are shown in the following table. Table 45-2. UART—Detailed signal descriptions Signal I/O Description CTS I Clear to send. Indicates whether the UART can start transmitting data when flow control is enabled. State meaning Asserted—Data transmission can start. Negated—Data transmission cannot start. Timing Assertion—When transmitting device's RTS asserts.
PAGE 1046
Memory map and registers 45.3 Memory map and registers This section provides a detailed description of all memory and registers. Accessing reserved addresses within the memory map results in a transfer error. None of the contents of the implemented addresses are modified as a result of that access. Only byte accesses are supported.
PAGE 1047
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_A00E UART Infrared Register (UART0_IR) 8 R/W 00h 45.3.15/ 1071 4006_A010 UART FIFO Parameters (UART0_PFIFO) 8 R/W See section 45.3.16/ 1072 4006_A011 UART FIFO Control Register (UART0_CFIFO) 8 R/W 00h 45.3.17/ 1074 4006_A012 UART FIFO Status Register (UART0_SFIFO) 8 R/W C0h 45.3.
PAGE 1048
Memory map and registers UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_A024 UART CEA709.1-B Beta1 Timer (UART0_B1T) 8 R/W 00h 45.3.35/ 1088 4006_A025 UART CEA709.1-B Secondary Delay Timer High (UART0_SDTH) 8 R/W 00h 45.3.36/ 1089 4006_A026 UART CEA709.1-B Secondary Delay Timer Low (UART0_SDTL) 8 R/W 00h 45.3.37/ 1089 4006_A027 UART CEA709.1-B Preamble (UART0_PRE) 8 R/W 00h 45.3.
PAGE 1049
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_B006 UART Control Register 3 (UART1_C3) 8 R/W 00h 45.3.7/ 1063 4006_B007 UART Data Register (UART1_D) 8 R/W 00h 45.3.8/ 1065 4006_B008 UART Match Address Registers 1 (UART1_MA1) 8 R/W 00h 45.3.9/ 1066 4006_B009 UART Match Address Registers 2 (UART1_MA2) 8 R/W 00h 45.3.
PAGE 1050
Memory map and registers UART memory map (continued) Absolute address (hex) Register name 4006_B01B UART 7816 Wait Parameter Register (UART1_WP7816T1) 8 4006_B01C UART 7816 Wait N Register (UART1_WN7816) 4006_B01D Width Access (in bits) Reset value Section/ page R/W 0Ah 45.3.27/ 1083 8 R/W 00h 45.3.28/ 1084 UART 7816 Wait FD Register (UART1_WF7816) 8 R/W 01h 45.3.29/ 1084 4006_B01E UART 7816 Error Threshold Register (UART1_ET7816) 8 R/W 00h 45.3.
PAGE 1051
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_B030 UART CEA709.1-B Receive Indeterminate Time (UART1_RIDT) 8 R/W 00h 45.3.47/ 1096 4006_B031 UART CEA709.1-B Transmit Indeterminate Time (UART1_TIDT) 8 R/W 00h 45.3.48/ 1097 4006_C000 UART Baud Rate Registers: High (UART2_BDH) 8 R/W 00h 45.3.
PAGE 1052
Memory map and registers UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_C013 UART FIFO Transmit Watermark (UART2_TWFIFO) 8 R/W 00h 45.3.19/ 1076 4006_C014 UART FIFO Transmit Count (UART2_TCFIFO) 8 R 00h 45.3.20/ 1077 4006_C015 UART FIFO Receive Watermark (UART2_RWFIFO) 8 R/W 01h 45.3.21/ 1077 4006_C016 UART FIFO Receive Count (UART2_RCFIFO) 8 R 00h 45.3.
PAGE 1053
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UART memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4006_C028 UART CEA709.1-B Transmit Packet Length (UART2_TPL) 8 R/W 00h 45.3.39/ 1090 4006_C029 UART CEA709.1-B Interrupt Enable Register (UART2_IE) 8 R/W 00h 45.3.40/ 1091 4006_C02A UART CEA709.1-B WBASE (UART2_WB) 8 R/W 00h 45.3.41/ 1092 4006_C02B UART CEA709.1-B Status Register (UART2_S3) 8 R/W 00h 45.3.
PAGE 1054
Memory map and registers UARTx_BDH field descriptions Field 7 LBKDIE Description LIN Break Detect Interrupt Enable Enables the LIN break detect flag, LBKDIF, to generate interrupt requests based on the state of LBKDDMAS. 0 1 6 RXEDGIE 4–0 SBR LBKDIF interrupt requests enabled. RxD Input Active Edge Interrupt Enable Enables the receive input active edge, RXEDGIF, to generate interrupt requests. 0 1 5 Reserved LBKDIF interrupt requests disabled.
PAGE 1055
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_BDL field descriptions (continued) Field Description The baud rate for the UART is determined by the 13 SBR fields. See Baud rate generation for details. NOTE: • The baud rate generator is disabled until C2[TE] or C2[RE] is set for the first time after reset.The baud rate generator is disabled when SBR = 0.
PAGE 1056
Memory map and registers UARTx_C1 field descriptions (continued) Field Description 0 1 3 WAKE Receiver Wakeup Method Select Determines which condition wakes the UART: • Address mark in the most significant bit position of a received data character, or • An idle condition on the receive pin input signal. 0 1 2 ILT Normal—start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. Use—start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. Idle line wakeup. Address mark wakeup.
PAGE 1057
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.3.4 UART Control Register 2 (UARTx_C2) This register can be read or written at any time.
PAGE 1058
Memory map and registers UARTx_C2 field descriptions (continued) Field Description 0 1 2 RE Receiver Enable Enables the UART receiver. 0 1 1 RWU Transmitter off. Transmitter on. Receiver off. Receiver on. Receiver Wakeup Control This field can be set to place the UART receiver in a standby state. RWU automatically clears when an RWU event occurs, that is, an IDLE event when C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be cleared when C7816[ISO_7816E] is set.
PAGE 1059
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) NOTE • If the condition that results in the assertion of the flag, interrupt, or DMA request is not resolved prior to clearing the flag, the flag, and interrupt/DMA request, reasserts. For example, if the DMA or interrupt service routine fails to write sufficient data to the transmit buffer to raise it above the watermark level, the flag reasserts and generates another interrupt or DMA request.
PAGE 1060
Memory map and registers UARTx_S1 field descriptions (continued) Field Description 0 1 5 RDRF Receive Data Register Full Flag RDRF is set when the number of datawords in the receive buffer is equal to or more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the process of being received is not included in the count. RDRF is prevented from setting while S2[LBKDE] is set.
PAGE 1061
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_S1 field descriptions (continued) Field Description in the buffer that was received with noise unless the receive buffer has a depth of one. To clear NF, read S1 and then read D. When EN709 is set/enabled, noise flag is not set. 0 1 1 FE No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
PAGE 1062
Memory map and registers UARTx_S2 field descriptions Field 7 LBKDIF Description LIN Break Detect Interrupt Flag LBKDIF is set when LBKDE is set and a LIN break character is detected on the receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M] = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the last LIN break character. LBKDIF is cleared by writing a 1 to it. 0 1 6 RXEDGIF No LIN break character detected. LIN break character detected.
PAGE 1063
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_S2 field descriptions (continued) Field 2 BRK13 Description Break Transmit Character Length Determines whether the transmit break character is 10, 11, or 12 bits long, or 13 or 14 bits long. See for the length of the break character for the different configurations. The detection of a framing error is not affected by this field.
PAGE 1064
Memory map and registers UARTx_C3 field descriptions Field Description 7 R8 Received Bit 8 6 T8 Transmit Bit 8 R8 is the ninth data bit received when the UART is configured for 9-bit data format, that is, if C1[M] = 1 or C4[M10] = 1. T8 is the ninth data bit transmitted when the UART is configured for 9-bit data format, that is, if C1[M] = 1 or C4[M10] = 1. NOTE: If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.
PAGE 1065
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_C3 field descriptions (continued) Field Description Enables the framing error flag, S1[FE], to generate interrupt requests. 0 1 0 PEIE FE interrupt requests are disabled. FE interrupt requests are enabled. Parity Error Interrupt Enable Enables the parity error flag, S1[PF], to generate interrupt requests. 0 1 PF interrupt requests are disabled. PF interrupt requests are enabled. 45.3.
PAGE 1066
Memory map and registers Addresses: UART0_D is 4006_A000h base + 7h offset = 4006_A007h UART1_D is 4006_B000h base + 7h offset = 4006_B007h UART2_D is 4006_C000h base + 7h offset = 4006_C007h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 RT 0 0 0 0 UARTx_D field descriptions Field 7–0 RT Description Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register. 45.3.
PAGE 1067
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.3.10 UART Match Address Registers 2 (UARTx_MA2) These registers can be read and written at anytime. The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the associated C4[MAEN] field is set. If a match occurs, the following data is transferred to the data register. If a match fails, the following data is discarded.
PAGE 1068
Memory map and registers UARTx_C4 field descriptions (continued) Field Description See Match address operation for more information. 0 1 5 M10 All data received is transferred to the data buffer if MAEN1 is cleared. All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer.
PAGE 1069
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_C5 field descriptions (continued) Field Description 0 1 6 Reserved 5 RDMAS If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. This read-only field is reserved and always has the value zero.
PAGE 1070
Memory map and registers Addresses: UART0_ED is 4006_A000h base + Ch offset = 4006_A00Ch UART1_ED is 4006_B000h base + Ch offset = 4006_B00Ch UART2_ED is 4006_C000h base + Ch offset = 4006_C00Ch Bit Read Write Reset 7 6 5 NOISY PARITYE 0 0 4 3 2 1 0 0 0 0 0 0 0 0 UARTx_ED field descriptions Field 7 NOISY Description The current received dataword contained in D and C3[R8] was received with noise. 0 1 The dataword was received without noise. The data was received with noise.
PAGE 1071
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_MODEM field descriptions (continued) Field 3 RXRTSE Description Receiver request-to-send enable Allows the RTS output to control the CTS input of the transmitting device to prevent receiver overrun. NOTE: Do not set both RXRTSE and TXRTSE. 0 1 2 TXRTSPOL Transmitter request-to-send polarity Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the polarity of the receiver RTS.
PAGE 1072
Memory map and registers UARTx_IR field descriptions Field 7–3 Reserved 2 IREN Description This read-only field is reserved and always has the value zero. Infrared enable Enables/disables the infrared modulation/demodulation. 0 1 1–0 TNP IR disabled. IR enabled. Transmitter narrow pulse Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse. 00 01 10 11 3/16. 1/16. 1/32. 1/4. 45.3.
PAGE 1073
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_PFIFO field descriptions (continued) Field Description When this field is set, the built in FIFO structure for the transmit buffer is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this field is not set, the transmit buffer operates as a FIFO of depth one dataword regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared prior to changing this field.
PAGE 1074
Memory map and registers 45.3.17 UART FIFO Control Register (UARTx_CFIFO) This register provides the ability to program various control fields for FIFO operation. This register may be read or written at any time. Note that writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action to prevent unintended/ unpredictable behavior. Therefore, it is recommended that TE and RE be cleared prior to flushing the corresponding FIFO.
PAGE 1075
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_CFIFO field descriptions (continued) Field 0 RXUFE Description Receive FIFO Underflow Interrupt Enable When this field is set, the RXUF flag generates an interrupt to the host. 0 1 RXUF flag does not generate an interrupt to the host. RXUF flag generates an interrupt to the host. 45.3.
PAGE 1076
Memory map and registers UARTx_SFIFO field descriptions (continued) Field Description 0 1 1 TXOF Transmitter Buffer Overflow Flag Indicates that more data has been written to the transmit buffer than it can hold. This field will assert regardless of the value of CFIFO[TXOFE]. However, an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This flag is cleared by writing a 1. 0 1 0 RXUF No receive buffer overflow has occurred since the last time the flag was cleared.
PAGE 1077
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.3.20 UART FIFO Transmit Count (UARTx_TCFIFO) This is a read only register that indicates how many datawords are currently in the transmit buffer/FIFO. It may be read at any time.
PAGE 1078
Memory map and registers UARTx_RWFIFO field descriptions (continued) Field Description receive FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be greater than 0. 45.3.22 UART FIFO Receive Count (UARTx_RCFIFO) This is a read only register that indicates how many datawords are currently in the receive FIFO/buffer. It may be read at any time.
PAGE 1079
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_C7816 field descriptions Field 7–5 Reserved 4 ONACK Description This read-only field is reserved and always has the value zero. Generate NACK on Overflow When this field is set, the receiver automatically generates a NACK response if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems, this results in the transmitter resending the packet that overflowed until the retransmit threshold for that transmitter is reached.
PAGE 1080
Memory map and registers 45.3.24 UART 7816 Interrupt Enable Register (UARTx_IE7816) The IE7816 register controls which flags result in an interrupt being issued. This register is specific to 7816 functionality, the corresponding flags that drive the interrupts are not asserted when 7816E is not set/enabled. However, these flags may remain set if they are asserted while 7816E was set and not subsequently cleared. This register may be read or written to at any time.
PAGE 1081
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_IE7816 field descriptions (continued) Field 0 RXTE Description Receive Threshold Exceeded Interrupt Enable 0 1 The assertion of IS7816[RXT] does not result in the generation of an interrupt. The assertion of IS7816[RXT] results in the generation of an interrupt. 45.3.25 UART 7816 Interrupt Status Register (UARTx_IS7816) The IS7816 register provides a mechanism to read and clear the interrupt flags.
PAGE 1082
Memory map and registers UARTx_IS7816 field descriptions (continued) Field 5 BWT Description Block Wait Timer Interrupt Indicates that the block wait time, the time between the leading edge of first received character of a block and the leading edge of the last character the previously transmitted block, has exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
PAGE 1083
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.3.26 UART 7816 Wait Parameter Register (UARTx_WP7816T0) The WP7816 register contains constants used in the generation of various wait timer counters. To save register space, this register is used differently when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any time. This register must be written to only when C7816[ISO_7816E] is not set.
PAGE 1084
Memory map and registers UARTx_WP7816T1 field descriptions (continued) Field Description Used to calculate the value used for the CWT counter. It represents a value between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time and guard time parameters . 3–0 BWI Block Wait Time Integer(C7816[TTYPE] = 1) Used to calculate the value used for the BWT counter. It represent a value between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time and guard time parameters . 45.
PAGE 1085
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_WF7816 field descriptions Field 7–0 GTFD Description FD Multiplier Used as another multiplier in the calculation of WT and BWT. This value represents a number between 1 and 255. The value of 0 is invalid. This value is not used in baud rate generation. See Wait time and guard time parameters and Baud rate generation . 45.3.
PAGE 1086
Memory map and registers 45.3.31 UART 7816 Transmit Length Register (UARTx_TL7816) The TL7816 register is used to indicate the number of characters contained in the block being transmitted. This register is used only when C7816[TTYPE] = 1. This register may be read at anytime. This register must be written only when C2[TE] is not enabled.
PAGE 1087
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_C6 field descriptions (continued) Field Description 0 1 6 TX709 CEA709.1-B Transmit Enable Starts CEA709.1-B transmission. 0 1 5 CE CEA709.1-B is disabled. CEA709.1-B is enabled CEA709.1-B transmitter is disabled. CEA709.1-B transmitter is enabled. Collision Enable Enables the collision detect functionality. 0 1 4 CP Collision detect feature is disabled. Collision detect feature is enabled.
PAGE 1088
Memory map and registers 45.3.34 UART CEA709.
PAGE 1089
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.3.36 UART CEA709.
PAGE 1090
Memory map and registers 45.3.38 UART CEA709.1-B Preamble (UARTx_PRE) Addresses: UART0_PRE is 4006_A000h base + 27h offset = 4006_A027h UART1_PRE is 4006_B000h base + 27h offset = 4006_B027h UART2_PRE is 4006_C000h base + 27h offset = 4006_C027h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 PREAMBLE 0 0 0 0 UARTx_PRE field descriptions Field 7–0 PREAMBLE Description CEA709.
PAGE 1091
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.3.40 UART CEA709.
PAGE 1092
Memory map and registers UARTx_IE field descriptions (continued) Field 1 PSIE Description Preamble Start Interrupt Enable Interrupt enable for preamble start flag. 0 1 0 TXFIE Interrupt is disabled. Interrupt is enabled. Transmission Fail Interrupt Enable Interrupt enable for transmission fail flag. 0 1 Interrupt is disabled. Interrupt is enabled. 45.3.41 UART CEA709.
PAGE 1093
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_S3 field descriptions Field 7 PEF Description Preamble Error Flag Indicates that the received preamble has an error. If the received preamble length is greater than or less than the transmit preamble length, the preamble error flag is asserted. This flag is cleared by writing 1. 0 1 6 WBEF Wbase Expired Flag Indicates that the Wbase time period has expired after beta1 time slots. This flag is cleared by writing 1.
PAGE 1094
Memory map and registers UARTx_S3 field descriptions (continued) Field Description line code violation is transmitted on TX line immediately after the current byte or preamble transmission is finished, without waiting for completion of transmit packet length. If the transmission fail flag is asserted, C6[TX709] is cleared. This flag is cleared by writing 1. 0 1 Transmission continues normally. Transmission has failed. 45.3.43 UART CEA709.
PAGE 1095
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UARTx_S4 field descriptions (continued) Field 0 FE Description Framing Error Indicates that the received CEA709.1-B packet has finished at byte boundary. This flag is cleared by writing 1. 0 1 Received packet is byte bound. Received packet is not byte bound. 45.3.44 UART CEA709.
PAGE 1096
Memory map and registers UARTx_RPREL field descriptions (continued) Field Description Indicates the number of bit sync fields received in the preamble. 45.3.46 UART CEA709.
PAGE 1097
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.3.48 UART CEA709.1-B Transmit Indeterminate Time (UARTx_TIDT) Addresses: UART0_TIDT is 4006_A000h base + 31h offset = 4006_A031h UART1_TIDT is 4006_B000h base + 31h offset = 4006_B031h UART2_TIDT is 4006_C000h base + 31h offset = 4006_C031h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 TIDT 0 0 0 0 UARTx_TIDT field descriptions Field 7–0 TIDT Description CEA709.
PAGE 1098
Functional description 45.4.1.1 CEA709.1-B packet cycle The following figure illustrates the frame format and Differential Manchester encoding. Differential Manchester encoding requires that each transmitted bit includes a clock transition at the start of the bit period. This allows synchronization with the receiver. 1 0 1 1 1 0 0 1 Transmitter Enable Byte Sync Bit Sync Data+16bit CRC Line Code Beta1 SDT Figure 45-193.
PAGE 1099
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.4.1.2 Packet cycle and delay calculations Packet 1 2 Priority slots w 1 2 Packet Randomizing w i ndow Figure 45-195. CEA709.1-B packet cycle Predictive p-persistent CSMA is a technique for collision avoidance that randomizes channel access using knowledge of predicted load. It manages software using data and events reported by the hardware. Beta1 delay is a value set by the software.
PAGE 1100
Functional description Each node must maintain an estimation of the current channel backlog. Backlog calculation is managed by the layer two software. Initially, the backlog is set to one. The backlog is incremented on transmission by a value indicated in the frames backlog increment field. The backlog decrements under the following conditions: • • • • On waiting to transmit: If Wbase randomizing slots go by without channel activity. On receive: If a packet is received with a backlog increment of 0.
PAGE 1101
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 4. If a single noise event occurs, and it is possible to uniquely identify the noise event, then resynchronization takes place. Starting at sample 15 of the previous time bit period, five data samples are collected. The number and location of the samples are key to decide if an adjustment in time base is required. Table below lists the possible values and the actions associated with each possibility.
PAGE 1102
Functional description Sample Values (15,16,1,2,3) Action / Event SDDSS In this case, either multiple errors occurred, two or more noise, or two or more noise and a time shift. The most likely case is that samples 16 and 1 are noise. Therefore, no adjustment to time base is made. SDDSD The most likely case is noise for sample 2 and a time shift. Therefore, the time base is sped up by one.
PAGE 1103
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) Sample Values (15,16,1,2,3) Action / Event DDSDD It is most likely that sample 1 is noise. Therefore, the time base is sped up by two. Sample 15 becomes sample 1, sample 16 becomes sample 2, sample 1 becomes sample 3, sample 2 becomes sample 4, sample 3 becomes sample 5, and the next sample taken is sample 6. DDDSS In this case multiple errors occurred along with time shift. Therefore, no adjustment to time base is made.
PAGE 1104
Functional description To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. The following table summarizes the results of the preamble verification samples. Table 45-200. Preamble/ Data bit verification RT3, RT5, and RT7 samples Preamble verification 000 Yes 001 Yes 010 Yes 011 No 100 Yes 101 No 110 No 111 No If preamble verification is not successful, the RT clock is reset and a new search for a preamble begins.
PAGE 1105
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.4.1.5 Initial clock synchronization When operating with EN709 set, there are various times when initial clock synchronization is required. When the UART has just been enabled, there is clearly no system clock reference. Additionally, if a channel has remained idle for a significant period of time, such as the arbitration time between packets, substantial clock drift may have occurred in the system between nodes.
PAGE 1106
Functional description 4. If a valid edge is not identified before the delay time expires, and data is queued to be transmitted, the UART considers itself synchronized, and starts the preamble process. 5. If a valid edge is not identified before the delay time expires, and data is not queued to be transmitted, the UART continues attempting to locate a valid edge using the same process, and receives the incoming data packet like in step 3.
PAGE 1107
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) preamble completes, the preamble started interrupt is asserted when the UART starts transmitting the preamble. NOTE If the data buffer does not contain at least one byte of valid data and the transmit packet length register has been updated prior to the preamble completing, an underflow event will occur and TXEN is deasserted. The packet is terminated by transmitting line code violation. 45.4.1.
PAGE 1108
Functional description 45.4.
PAGE 1109
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.4.2.2 Transmission bit order When S2[MSBF] is set, the UART automatically transmits the MSB of the data word as the first bit after the start bit. Similarly, the LSB of the data word is transmitted immediately preceding the parity bit, or the stop bit if parity is not enabled. All necessary bit ordering is handled automatically by the module.
PAGE 1110
Functional description received. If a NACK is received, the transmitter resends the data, assuming that the number of retries for that character, that is, the number of NACKs received, is less than or equal to the value in ET7816[TXTHRESHOLD]. Hardware supports odd or even parity. When parity is enabled, the bit immediately preceding the stop bit is the parity bit. When the transmit shift register is not transmitting a frame, the transmit data output signal goes to the idle condition, logic 1.
PAGE 1111
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) As long as C2[SBK] is set, the transmitter logic continuously loads break characters into the transmit shift register. After the software clears C2[SBK], the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. Break bits are not supported when C7816[ISO_7816E] is set/enabled.
PAGE 1112
Functional description 45.4.2.6 Hardware flow control The transmitter supports hardware flow control by gating the transmission with the value of CTS. If the clear-to-send operation is enabled, the character is transmitted when CTS is asserted. If CTS is deasserted in the middle of a transmission with characters remaining in the receiver data buffer, the character in the shift register is sent and TXD remains in the mark state until CTS is reasserted.
PAGE 1113
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) C1 in transmission TXD data buffer write C1 1 C1 C2 C2 C3 Break C3 C4 Start Stop Break Break C4 C5 C5 CTS_B RTS_B 1. Cn = transmit characters Figure 45-199. Transmitter RTS and CTS timing diagram K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 Freescale Semiconductor, Inc.
PAGE 1114
Functional description 45.4.3 Receiver INTERNAL BUS BRFA4:0 RE RAF BAUDRATE GENERATOR STOP MODULE CLOCK DATA BUFFER VARIABLE 12-BIT RECEIVE SHIFT REGISTER START SBR12:0 RECEIVE CONTROL M M10 LBKDE MSBF RXINV SHIFT DIRECTION RxD LOOPS RSRC RECEIVER SOURCE CONTROL PE PT From Transmitter RxD PARITY LOGIC WAKEUP LOGIC IRQ / DMA LOGIC ACTIVE EDGE DETECT DMA Requests IRQ Requests To TxD 7816 LOGIC INFRARED LOGIC Figure 45-200. UART receiver block diagram 45.4.3.
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Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.4.3.2 Receiver bit ordering When S2[MSBF] is set, the receiver operates such that the first bit received after the start bit is the MSB of the dataword. Similarly, the bit received immediately preceding the parity bit, or the stop bit if parity is not enabled, is treated as the LSB for the dataword. All necessary bit ordering is handled automatically by the module.
PAGE 1116
Functional description has no stop bit. S1[FE] is set at the same time that received data is placed in the receive data buffer. Framing errors are not supported when C7816[ISO7816E] is set/enabled. However, if S1[FE] is set, data will not be received when C7816[ISO7816E] is set. 45.4.3.5 Receiving break characters The UART recognizes a break character when a start bit is followed by eight, nine, or ten logic 0 data bits and a logic 0 where the stop bit should be.
PAGE 1117
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.4.3.6 Hardware flow control To support hardware flow control, the receiver can be programmed to automatically deassert and assert RTS. • RTS remains asserted until the transfer is complete, even if the transmitter is disabled midway through a data transfer. See Transceiver driver enable using RTS for more details.
PAGE 1118
Functional description 45.4.3.7 Infrared decoder The infrared decoder converts the received character from the IrDA format to the NRZ format used by the receiver. It also has a 16-RT clock counter that filters noise and indicates when a 1 is received. 45.4.3.7.1 Start bit detection When S2[RXINV] is cleared, the first rising edge of the received character corresponds to the start bit. The infrared decoder resets its counter. At this time, the receiver also begins its start bit detection process.
PAGE 1119
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic 0. As the receiver samples an incoming frame, it resynchronizes the RT clock on any valid falling edge within the frame. Resynchronization within frames corrects a misalignment between transmitter bit times and receiver bit times. 45.
PAGE 1120
Functional description 45.4.3.8.2 Fast data tolerance The following figure shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. IDLE OR NEXT FRAME STOP RT16 RT15 RT14 RT13 RT12 DATA SAMPLES RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RECEIVER RT CLOCK Figure 45-203.
PAGE 1121
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.4.3.9.1 Idle input line wakeup (C1[WAKE] = 0) In this wakeup method, an idle condition on the unsynchronized receiver input signal clears C2[RWU] and wakes the UART. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow.
PAGE 1122
Functional description 45.4.3.9.3 Match address operation Match address operation is enabled when C4[MAEN1] or C4[MAEN2] is set. In this function, a frame received by the RX pin with a logic 1 in the bit position immediately preceding the stop bit is considered an address and is compared with the associated MA1 or MA2 register. The frame is transferred to the receive buffer, and S1[RDRF] is set, only if the comparison matches.
PAGE 1123
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) UART baud rate = UART module clock / (16 × (SBR[12:0] + BRFD)) The following table lists some examples of achieving target baud rates with a module clock frequency of 10.2 MHz, with and without fractional fine adjustment. Table 45-204. Baud rates (example: module clock = 10.2 MHz) Bits SBR (decimal) Bits BRFA BRFD value Receiver Transmitter Error clock (Hz) Target Baud rate clock (Hz) (%) 17 00000 0 600,000.0 37,500.0 38,400 2.
PAGE 1124
Functional description Table 45-205. Baud rate fine adjust (continued) BRFA Baud Rate Fractional Divisor (BRFD) 01110 14/32 = 0.4375 01111 15/32 = 0.46875 10000 16/32 = 0.5 10001 17/32 = 0.53125 10010 18/32 = 0.5625 10011 19/32 = 0.59375 10100 20/32 = 0.625 10101 21/32 = 0.65625 10110 22/32 = 0.6875 10111 23/32 = 0.71875 11000 24/32 = 0.75 11001 25/32 = 0.78125 11010 26/32 = 0.8125 11011 27/32 = 0.84375 11100 28/32 = 0.875 11101 29/32 = 0.90625 11110 30/32 = 0.
PAGE 1125
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) Table 45-206. Configuration of 8-bit data format UART_C1[PE] Start Data Address Parity Stop bit bits bits bits bit 1 8 0 0 1 0 1 1 1 0 0 1 7 11 1 1 7 0 1. The address bit identifies the frame as an address character. See Receiver wakeup. 45.4.5.2 Nine-bit configuration When C1[M] is set and C4[M10] is cleared, the UART is configured for 9-bit data characters.
PAGE 1126
Functional description 2. The address bit identifies the frame as an address character. Note Unless in 9-bit mode with M10 set, do not use address mark wakeup with parity enabled. 45.4.5.3 Timing examples Timing examples of these configurations in the NRZ mark/space data format are illustrated in the following figures. The timing examples show all of the configurations in the following sub-sections along with the LSB and MSB first variations. 45.4.5.3.
PAGE 1127
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) ADDRESS MARK START BIT 8 BIT 7 BIT BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 START BIT 0 STOP BIT BIT Figure 45-209. Nine bits of data with MSB first 45.4.5.3.4 Nine-bit format with parity enabled START BIT 0 BIT BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 START BIT 7 PARITY STOP BIT BIT Figure 45-210.
PAGE 1128
Functional description Enable single wire operation by setting C1[LOOPS] and the receiver source field, C1[RSRC]. Setting C1[LOOPS] disables the path from the unsynchronized receiver input signal to the receiver. Setting C1[RSRC] connects the receiver input to the output of the TXD pin driver. Both the transmitter and receiver must be enabled (C2[TE] = 1 and C2[RE] = 1). When C7816[ISO_7816EN] is set, it is not required that both C2[TE] and C2[RE] are set. 45.4.
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Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) The term elemental time unit (ETU) is frequently used in the context of ISO-7816. This concept is used to relate the frequency that the system (UART) is running at and the frequency that data is being transmitted and received. One ETU represents the time it takes to transmit or receive a single bit. For example, a standard 7816 packet, excluding any guard time or NACK elements is 10 ETUs (start bit, 8 data bits, and a parity bit).
PAGE 1130
Functional description received, which is not a valid initial character, is ignored and all flags resulting from the invalid data are blocked from asserting. If C7816[ANACK] is set, a NACK is returned for invalid received initial characters and an RXT interrupt is generated as programmed. 45.4.8.2 Protocol T = 0 When T = 0 protocol is selected, a relatively complex error detection scheme is used. Data characters are formatted as illustrated in the following figure.
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Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) ISO 7816 FORMAT (T=1) START BIT 0 BIT PARITY BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT NEXT START STOP BIT BIT Figure 45-217. ISO 7816 T=1 data format The smallest data unit that is transferred is a block. A block is made up of several data characters and may vary in size depending on the block type. The UART does not provide a mechanism to decode the block type. As part of the block, an LRC or CRC is included.
PAGE 1132
Functional description transmission or reception. Block guard time (BGT) is the minimum allowable time between the leading edges of two consecutive characters in opposite directions, that is, transmission then reception or reception then transmission. The GT and WT counters reset whenever C7816[TTYPE] = 1 or C7816[ISO_7816E] = 0 or a new dataword start bit has been received or transmitted as specified by the counter descriptions.
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Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.4.8.6 UART restrictions in ISO-7816 operation Due to the flexibility of the UART module, there are several features and interrupts that are not supported while running in ISO-7816 mode. These restrictions are documented within the register field definitions. 45.4.
PAGE 1134
Reset 45.4.9.2 Infrared receive decoder The infrared receive block converts data from the RXD signal to the receive shift register. A narrow pulse is expected for each zero received and no pulse is expected for each one received. A narrow high pulse is expected for a zero bit when S2[RXINV] is cleared, while a narrow low pulse is expected for a zero bit when S2[RXINV] is set. This receive decoder meets the edge jitter requirement as defined by the IrDA serial infrared physical layer specification. 45.
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Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) Table 45-210. UART interrupt sources (continued) Interrupt Source Flag Local enable DMA select Receiver WT WTWE - Receiver CWT CWTE - Receiver BWT BWTE - Receiver INITD INITDE - Receiver TXT TXTE - Receiver RXT RXTE - Receiver GTV GTVE - 45.6.1 RXEDGIF description S2[RXEDGIF] is set when an active edge is detected on the RxD pin. Therefore, the active edge can be detected only when in two wire mode.
PAGE 1136
DMA operation 45.6.1.3 Exit from low-power modes The receive input active edge detect circuit is still active on low power modes (Wait and Stop). An active edge on the receive input brings the CPU out of low power mode if the interrupt is not masked (S2[RXEDGIF]=1). 45.7 DMA operation In the transmitter, S1[TDRE] can be configured to assert a DMA transfer request. In the receiver, S1[RDRF], can be configured to assert a DMA transfer request.
PAGE 1137
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) depth of one. This is the default/reset behavior of the module and can be adjusted using the PFIFO[RXFE] and PFIFO[TXFE] bits. Individual watermark levels are also provided for transmit and receive. There are multiple ways to ensure that a data block, which is a set of characters, has completed transmission. These methods include: 1. Set TXFIFO[TXWATER] to 0. TDRE asserts when there is no further data in the transmit buffer.
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Application information 6. Write to set up interrupt enable fields desired (C3[ORIE], C3[NEIE], C3[PEIE], and C3[FEIE]) 7. Write to set C4[MAEN1] = 0 and C4[MAEN2] = 0. 8. Write to C5 register and configure DMA control register fields as desired for application. 9. Write to set C7816[INIT] = 1,C7816[ TTYPE] = 0, and C7816[ISO_7816E] = 1. Program C7816[ONACK] and C7816[ANACK] as desired. 10. Write to IE7816 to set interrupt enable parameters as desired. 11. Write to ET7816 and set as desired. 12.
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Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 45.8.2.2 Transmission procedure for (C7816[TTYPE] = 1) When the protocol selected is C7816[TTYPE] = 1, data is transferred in blocks. Before starting a transmission, the software must write the size, in number of bytes, for the Information Field portion of the block into TLEN. If a CRC is being transmitted for the block, the value in TLEN must be one more than the size of the information field.
PAGE 1140
Application information 3. Repeat step 2 for each subsequent transmission. Note During normal operation, S1[TDRE] is set when the shift register is loaded with the next data to be transmitted from the transmit buffer and the number of datawords contained in the transmit buffer is less than or equal to the value in TWFIFO[TXWATER]. This occurs 9/16ths of a bit time after the start of the stop bit of the previous frame.
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Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) 1. Remove data from the receive data buffer. This could be done by reading data from the data buffer and processing it if the data in the FIFO was still valuable when the overrun event occurred, or using CFIFO[RXFLUSH] to clear the buffer. 2. Clear S1[OR]. Note that if data was cleared using CFIFO[RXFLUSH], then clearing S1[OR] will result in SFIFO[RXUF] asserting.
PAGE 1142
Application information ET7816[RXTHRESHOLD] value will be incremented by one. However, if sufficient space now exists to write the received data which was NACK'ed, S1[OR] will be blocked and kept from asserting. 45.8.6 Match address registers The two match address registers allow a second match address function for a broadcast or general call address to the serial bus, as an example. 45.8.7 Modem feature This section describes the modem features. 45.8.7.
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Chapter 45 Universal Asynchronous Receiver/Transmitter (UART) RS-485 TRANSCEIVER UART TRANSMITTER TXD DI RTS_B DE RXD RECEIVER Y DRIVER A RO RE_B Z RECEIVER B Figure 45-219. Transceiver driver enable using RTS In the figure, the receiver enable signal is asserted. Another option for this connection is to connect RTS_B to both DE and RE_B. The transceiver's receiver is disabled while driving. A pullup can pull RXD to a non-floating value during this time.
PAGE 1144
Application information If the intent of clearing the interrupt is such that it does not reassert, the interrupt service routine must remove or clear the condition that originally caused the interrupt to assert prior to clearing the interrupt. There are multiple ways that this can be accomplished, including ensuring that an event that results in the wait timer resetting occurs, such as, the transmission of another packet. 45.8.
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Chapter 46 Synchronous Audio Interface (SAI) 46.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The I2S (or I2S) module provides a synchronous audio interface (SAI) that supports fullduplex serial interfaces with frame synchronization such as I2S, AC97, and codec/DSP interfaces. 46.1.
PAGE 1146
Introduction Figure 46-1. I2S/SAI block diagram 46.1.3 Modes of operation The module operates in these MCU power modes: Run mode, stop modes, low-leakage modes, and Debug mode. 46.1.3.1 Run mode In Run mode, the SAI transmitter and receiver operate normally. 46.1.3.
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Chapter 46 Synchronous Audio Interface (SAI) In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitter is disabled after completing the current transmit frame, and, if the Receiver Stop Enable (RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receive frame. Entry into Stop mode is prevented–not acknowledged–while waiting for the transmitter and receiver to be disabled at the end of the current frame. 46.1.3.
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Memory map and register definition 46.3 Memory map and register definition A read or write access to an address after the last register will result in a bus error. I2S memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_F000 SAI Transmit Control Register (I2S0_TCSR) 32 R/W 0000_0000h 46.3.1/ 1149 4002_F004 SAI Transmit Configuration 1 Register (I2S0_TCR1) 32 R/W 0000_0000h 46.3.
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Chapter 46 Synchronous Audio Interface (SAI) I2S memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4002_F0C0 SAI Receive FIFO Register (I2S0_RFR0) 32 R 0000_0000h 46.3.17/ 1166 4002_F0E0 SAI Receive Mask Register (I2S0_RMR) 32 R/W 0000_0000h 46.3.18/ 1167 4002_F100 SAI MCLK Control Register (I2S0_MCR) 32 R/W 0000_0000h 46.3.19/ 1168 4002_F104 SAI MCLK Divide Register (I2S0_MDR) 32 R/W 0000_0000h 46.3.20/ 1169 46.3.
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Memory map and register definition I2Sx_TCSR field descriptions (continued) Field Description 0 1 28 BCE Bit Clock Enable Enables the transmit bit clock, separately from the TE. This field is automatically set whenever TE is set. When software clears this field, the transmit bit clock remains enabled, and this bit remains set, until the end of the current frame. 0 1 27–26 Reserved 25 FR FIFO Reset Resets the FIFO pointers. Reading this field will always return zero.
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Chapter 46 Synchronous Audio Interface (SAI) I2Sx_TCSR field descriptions (continued) Field Description 0 1 16 FRF FIFO Request Flag Indicates that the number of words in an enabled transmit channel FIFO is less than or equal to the transmit FIFO watermark. 0 1 15–13 Reserved 12 WSIE Word Start Interrupt Enable Enables/disables word start interrupts. Enables/disables sync error interrupts. Enables/disables FIFO error interrupts. Disables the interrupt. Enables the interrupt.
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Memory map and register definition I2Sx_TCSR field descriptions (continued) Field Description 0 1 0 FRDE Disables the DMA request. Enables the DMA request. FIFO Request DMA Enable Enables/disables DMA requests. 0 1 Disables the DMA request. Enables the DMA request. 46.3.
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Chapter 46 Synchronous Audio Interface (SAI) I2Sx_TCR2 field descriptions Field 31–30 SYNC Description Synchronous Mode Configures between asynchronous and synchronous modes of operation. When configured for a synchronous mode of operation, the receiver must be configured for asynchronous operation. 00 01 10 11 29 BCS Bit Clock Swap When the SAI is in asynchronous mode and this field is set to 1, the transmitter is clocked by the receiver bit clock.
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Memory map and register definition I2Sx_TCR2 field descriptions (continued) Field Description 7–0 DIV Bit Clock Divide Divides down the audio master clock to generate the bit clock when configured for an internal bit clock. The division value is (DIV + 1) * 2. 46.3.4 SAI Transmit Configuration 3 Register (I2Sx_TCR3) This register must not be altered when TCSR[TE] is set.
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Chapter 46 Synchronous Audio Interface (SAI) 46.3.5 SAI Transmit Configuration 4 Register (I2Sx_TCR4) This register must not be altered when TCSR[TE] is set.
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Memory map and register definition I2Sx_TCR4 field descriptions (continued) Field Description 0 FSD Frame Sync Direction Configures the direction of the frame sync. 0 1 Frame sync is generated externally in Slave mode. Frame sync is generated internally in Master mode. 46.3.6 SAI Transmit Configuration 5 Register (I2Sx_TCR5) This register must not be altered when TCSR[TE] is set.
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Chapter 46 Synchronous Audio Interface (SAI) 46.3.
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Memory map and register definition 46.3.9 SAI Transmit Mask Register (I2Sx_TMR) This register is double-buffered and updates: 1. When TCSR[TE] is first set 2. At the end of each frame. This allows the masked words in each frame to change from frame to frame.
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Chapter 46 Synchronous Audio Interface (SAI) I2Sx_RCSR field descriptions Field 31 RE Description Receiver Enable Enables/disables the receiver. When software clears this field, the receiver remains enabled, and this bit remains set, until the end of the current frame. 0 1 30 STOPE Stop Enable Configures receiver operation in Stop mode. This bit is ignored and the receiver is disabled in all lowleakage stop modes. 0 1 29 DBGE Enables/disables receiver operation in Debug mode.
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Memory map and register definition I2Sx_RCSR field descriptions (continued) Field Description 0 1 19 SEF Sync Error Flag Indicates that an error in the externally-generated frame sync has been detected. Write a logic 1 to this field to clear this flag. 0 1 18 FEF Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to this field to clear this flag. Indicates that an enabled receive FIFO is full.
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Chapter 46 Synchronous Audio Interface (SAI) I2Sx_RCSR field descriptions (continued) Field Description Enables/disables FIFO warning interrupts. 0 1 8 FRIE Disables the interrupt. Enables the interrupt. FIFO Request Interrupt Enable Enables/disables FIFO request interrupts. 0 1 Disables the interrupt. Enables the interrupt. 7–5 Reserved This read-only field is reserved and always has the value zero. 4–2 Reserved This read-only field is reserved and always has the value zero.
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Memory map and register definition 46.3.12 SAI Receive Configuration 2 Register (I2Sx_RCR2) This register must not be altered when RCSR[RE] is set.
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Chapter 46 Synchronous Audio Interface (SAI) I2Sx_RCR2 field descriptions (continued) Field Description 25 BCP Bit Clock Polarity Configures the polarity of the bit clock. 0 1 24 BCD Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. Bit Clock Direction Configures the direction of the bit clock. 0 1 23–8 Reserved Bit clock is generated externally in Slave mode.
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Memory map and register definition I2Sx_RCR3 field descriptions (continued) Field Description Configures which word the start of word flag is set. The value written should be one less than the word number (for example, write zero to configure for the first word in the frame). When configured to a value greater than the Frame Size field, then the start of word flag is never set. 46.3.14 SAI Receive Configuration 4 Register (I2Sx_RCR4) This register must not be altered when RCSR[RE] is set.
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Chapter 46 Synchronous Audio Interface (SAI) I2Sx_RCR4 field descriptions (continued) Field Description 2 Reserved This read-only field is reserved and always has the value zero. 1 FSP Frame Sync Polarity Configures the polarity of the frame sync. 0 1 0 FSD Frame sync is active high. Frame sync is active low. Frame Sync Direction Configures the direction of the frame sync. 0 1 Frame Sync is generated externally in Slave mode. Frame Sync is generated internally in Master mode. 46.3.
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Memory map and register definition I2Sx_RCR5 field descriptions (continued) Field Description 12–8 FBT First Bit Shifted Configures the bit index for the first bit received for each word in the frame. If configured for MSB First, the index of the next bit received is one less than the current bit received. If configured for LSB First, the index of the next bit received is one more than the current bit received.
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Chapter 46 Synchronous Audio Interface (SAI) I2Sx_RFRn field descriptions Field Description 31–19 Reserved This read-only field is reserved and always has the value zero. 18–16 WFP Write FIFO Pointer FIFO write pointer for receive data channel. 15–3 Reserved This read-only field is reserved and always has the value zero. 2–0 RFP Read FIFO Pointer FIFO read pointer for receive data channel. 46.3.18 SAI Receive Mask Register (I2Sx_RMR) This register is double-buffered and updates: 1.
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Memory map and register definition 46.3.19 SAI MCLK Control Register (I2Sx_MCR) The MCLK Control Register (MCR) controls the clock source and direction of the audio master clock.
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Chapter 46 Synchronous Audio Interface (SAI) 46.3.20 SAI MCLK Divide Register (I2Sx_MDR) The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the MDR can be changed when the MCLK divider clock is enabled, additional writes to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK divided clock is disabled do not set MCR[DUF].
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Functional description 46.4.1.1 Audio master clock The audio master clock is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. The transmitter and receiver can independently select between the bus clock and up to three audio master clocks to generate the bit clock. Each SAI peripheral can control the input clock selection, pin direction and divide ratio of one audio master clock.
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Chapter 46 Synchronous Audio Interface (SAI) 46.4.1.3 Bus clock The bus clock is used by the control and configuration registers and to generate synchronous interrupts and DMA requests. 46.4.2 SAI resets The SAI is asynchronously reset on system reset. The SAI has a software reset and a FIFO reset. 46.4.2.1 Software reset The SAI transmitter includes a software reset that resets all transmitter internal logic, including the bit clock generation, status flags, and FIFO pointers.
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Functional description 46.4.3.1 Synchronous mode The SAI transmitter and receiver can be configured to operate with synchronous bit clock and frame sync. If the transmitter bit clock and frame sync are to be used by both the transmitter and receiver: • The transmitter must be configured for asynchronous operation and the receiver for synchronous operation. • In synchronous mode, the receiver is enabled only when both the transmitter and receiver are enabled.
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Chapter 46 Synchronous Audio Interface (SAI) • Frame length from 1 to 16 words per frame • Word length to support 8 to 32 bits per word • First word length and remaining word lengths can be configured separately • Can be configured for MSB first or LSB first These configuration options cannot be changed after the SAI transmitter or receiver is enabled. 46.4.5 Data FIFO 46.4.5.1 Data alignment Each transmit and receive channel includes a FIFO of size 4 × 32-bit.
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Data FIFO Figure 46-52. SAI first bit shifted, MSB first 46.4.5.2 FIFO pointers When writing to a TDR, the WFP of the corresponding TFR increments after each valid write. The SAI supports 8-bit and 16-bit writes to TDR for transmitting 8-bit and 16-bit data respectively. Writes to a TDR are ignored if the corresponding bit of TCR3[TCE] is clear or if the FIFO is full.
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Chapter 46 Synchronous Audio Interface (SAI) The RMR causes the received data for each selected word to be discarded and not written to the receive FIFO. 46.4.7 Interrupts and DMA requests The SAI transmitter and receiver generate separate interrupts and separate DMA requests, but support the same status flags. Asynchronous versions of the transmitter and receiver interrupts are generated to wake up the CPU from stop mode. 46.4.7.
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Data FIFO 46.4.7.3 FIFO error flag The transmit FIFO error flag is set when the any of the enabled transmit FIFOs underflow. After it is set, all enabled transmit channels repeat the last valid word read from the transmit FIFO until TCSR[FEF] is cleared and the next transmit frame starts. All enabled transmit FIFOs must be reset and initialized with new data before TCSR[FEF] is cleared. RCSR[FEF] is set when the any of the enabled receive FIFOs overflow.
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Chapter 47 General-Purpose Input/Output (GPIO) 47.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The general-purpose input and output (GPIO) module communicates to the processor core via a zero wait state interface for maximum pin performance. The GPIO registers support 8-bit, 16-bit or 32-bit accesses.
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Introduction Table 47-1. Modes of operation Modes of operation Description Run The GPIO module operates normally. Wait The GPIO module operates normally. Stop The GPIO module is disabled. Debug The GPIO module operates normally. 47.1.3 GPIO signal descriptions Table 47-2.
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Chapter 47 General-Purpose Input/Output (GPIO) 47.1.3.1 Detailed signal description Table 47-3. GPIO interface-detailed signal descriptions Signal I/O Description PORTA31–PORTA0 I/O General-purpose input/output PORTB31–PORTB0 State meaning Asserted: The pin is logic 1. PORTC31–PORTC0 Deasserted: The pin is logic 0. PORTD31–PORTD0 Timing PORTE31–PORTE0 Assertion: When output, this signal occurs on the risingedge of the system clock.
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Memory map and register definition GPIO memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 0000_0000h 47.2.4/ 1183 400F_F00C Port Toggle Output Register (GPIOA_PTOR) 32 W (always reads zero) 400F_F010 Port Data Input Register (GPIOA_PDIR) 32 R 0000_0000h 47.2.5/ 1184 400F_F014 Port Data Direction Register (GPIOA_PDDR) 32 R/W 0000_0000h 47.2.6/ 1185 400F_F040 Port Data Output Register (GPIOB_PDOR) 32 R/W 0000_0000h 47.2.
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Chapter 47 General-Purpose Input/Output (GPIO) GPIO memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 32 R/W 0000_0000h 47.2.1/ 1182 32 W (always reads zero) 0000_0000h 47.2.2/ 1182 32 W (always reads zero) 0000_0000h 47.2.3/ 1183 400F_F0CC Port Toggle Output Register (GPIOD_PTOR) 32 W (always reads zero) 0000_0000h 47.2.4/ 1183 400F_F0D0 Port Data Input Register (GPIOD_PDIR) 32 R 0000_0000h 47.2.
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Memory map and register definition 47.2.1 Port Data Output Register (GPIOx_PDOR) This register configures the logic levels that are driven on each general-purpose output pins.
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Chapter 47 General-Purpose Input/Output (GPIO) GPIOx_PSOR field descriptions (continued) Field Description 0 1 Corresponding bit in PDORn does not change. Corresponding bit in PDORn is set to logic 1. 47.2.3 Port Clear Output Register (GPIOx_PCOR) This register configures whether to clear the fields of PDOR.
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Memory map and register definition GPIOx_PTOR field descriptions Field Description 31–0 PTTO Port Toggle Output Writing to this register will update the contents of the corresponding bit in the PDOR as follows: 0 1 Corresponding bit in PDORn does not change. Corresponding bit in PDORn is set to the inverse of its existing logic state. 47.2.
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Chapter 47 General-Purpose Input/Output (GPIO) 47.2.6 Port Data Direction Register (GPIOx_PDDR) The PDDR configures the individual port pins for input or output.
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Functional description 47.3.2 General-purpose output The logic state of each pin can be controlled via the pin data output registers and port data direction registers, provided the pin is configured for the GPIO function. The following table depicts the conditions for a pin to be configured as input/output. If Then A pin is configured for the GPIO function and the corresponding data output enable register bit is clear. The pin is configured as an input.
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Chapter 48 Touch sense input (TSI) 48.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The touch sensing input (TSI) module provides capacitive touch sensing detection with high sensitivity and enhanced robustness. Each TSI pin implements the capacitive measurement of an electrode having individual programmable detection thresholds and result registers.
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Overview • Compensate temperature and supply voltage variations • Stand alone operation not requiring any external crystal even in low power modes • Configurable integration of each electrode capacitance measurement from 1 to 4096 periods • Programmable Electrode Oscillator and TSI Reference Oscillator allowing high sensitivity, small scan time and low power functionality. • Only uses one pin per electrode implementation with no external hardware required 48.
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Chapter 48 Touch sense input (TSI) 48.3.1 Electrode capacitance measurement unit The electrode capacitance measurement unit senses the capacitance of a TSI pin and outputs a 16-bit result. This module is based in dual oscillator architecture. One oscillator is connected to the external electrode array and oscillates according to the electrode capacitance, while the other according to an internal reference capacitor.
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Modes of operation scan period during low power mode, so contributing to smaller average power consumption. The TSI, in low power mode, has the capability to wake up the CPU upon an electrode capacitance change. When the CPU wakes, the TSI enters active mode, and a shorter scan period can provide a faster response time and more robust touch detection. Apart from the periodical mode, the electrode scan unit also allows software triggering of the electrode scans.
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Chapter 48 Touch sense input (TSI) Table 48-1.
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Modes of operation capacitance measurements. The scan period is defined by GENCS[LPSCNITV] . Two low power clock sources are available in the TSI low power mode, LPOCLK and VLPOSCCLK, being selected by the GENCS[LPCLKS]. In low power mode the TSI interrupt can also be configured as end-of-scan or out-ofrange and the GENCS[TSIIEN] must be set in order to generate these interrupts. The TSI interrupt causes the exit of the low power mode and entrance in the active mode, and the MCU also wakes up.
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Chapter 48 Touch sense input (TSI) 48.5 TSI signal descriptions The TSI module has up to 16 external pins for touch sensing. The table below itemizes all the TSI external pins. Table 48-2. TSI signal descriptions Signal TSI_IN[15:0] Description I/O TSI capacitive pins. Switchable driver that connects directly to the electrode pins TSI[15:0] can operate as GPIO pins I/O 48.5.
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Memory map and register definition TSI memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_5104 Counter Register (TSI0_CNTR3) 32 R 0000_0000h 48.6.5/ 1203 4004_5108 Counter Register (TSI0_CNTR5) 32 R 0000_0000h 48.6.5/ 1203 4004_510C Counter Register (TSI0_CNTR7) 32 R 0000_0000h 48.6.5/ 1203 4004_5110 Counter Register (TSI0_CNTR9) 32 R 0000_0000h 48.6.
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Chapter 48 Touch sense input (TSI) 48.6.
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Memory map and register definition TSIx_GENCS field descriptions (continued) Field Description 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 23–19 NSCN 10 ms scan interval 15 ms scan interval 20 ms scan interval 30 ms scan interval 40 ms scan interval 50 ms scan interval 75 ms scan interval 100 ms scan interval 125 ms scan interval 150 ms scan interval 200 ms scan interval 300 ms scan interval 400 ms scan interval 500 ms scan interval Number of Consecutive Scans per Electrode el
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Chapter 48 Touch sense input (TSI) TSIx_GENCS field descriptions (continued) Field Description 11101 11110 11111 18–16 PS 30 times per electrode 31 times per electrode 32 times per electrode Electrode Oscillator prescaler. .
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Memory map and register definition TSIx_GENCS field descriptions (continued) Field Description 0 1 TSI module is disabled TSI module is enabled 6 TSIIE Touch Sensing Input Interrupt Module Enable 5 ERIE Error Interrupt Enable 0 1 Interrupt from TSI is disabled Interrupt from TSI is enabled Caused either by a Short or Overrun Error. 0 1 4 ESOR Interrupt disabled for error. Interrupt enabled for error. End-of-Scan or Out-of-Range Interrupt select 0 1 Out-of-Range interrupt is allowed.
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Chapter 48 Touch sense input (TSI) TSIx_SCANC field descriptions Field 31–28 Reserved 27–24 REFCHRG 23–20 Reserved 19–16 EXTCHRG 15–8 SMOD 7–6 Reserved Description This read-only field is reserved and always has the value zero. Ref OSC Charge Current select 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 2 µA charge current. 4 µA charge current. 6 µA charge current. 8 µA charge current. 10 µA charge current. 12 µA charge current. 14 µA charge current.
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Memory map and register definition TSIx_SCANC field descriptions (continued) Field Description 5 Reserved This read-only field is reserved and always has the value zero. 4–3 AMCLKS Active Mode Clock Source 2–0 AMPSC Active Mode Prescaler 00 01 10 11 LPOSCCLK MCGIRCLK. OSCERCLK. Not valid. 000 001 010 011 100 101 110 111 Input Clock Source divided by 1. Input Clock Source divided by 2. Input Clock Source divided by 4. Input Clock Source divided by 8. Input Clock Source divided by 16.
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Chapter 48 Touch sense input (TSI) TSIx_PEN field descriptions (continued) Field Description 0111 1000 1001 1010 1011 1100 1101 1110 1111 TSI_IN[7] is active in low power mode. TSI_IN[8] is active in low power mode. TSI_IN[9] is active in low power mode. TSI_IN[10] is active in low power mode. TSI_IN[11] is active in low power mode. TSI_IN[12] is active in low power mode. TSI_IN[13] is active in low power mode. TSI_IN[14] is active in low power mode. TSI_IN[15] is active in low power mode.
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Memory map and register definition TSIx_PEN field descriptions (continued) Field Description 0 1 The corresponding pin is not used by TSI. The corresponding pin is used by TSI.
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Chapter 48 Touch sense input (TSI) 48.6.
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Functional descriptions 48.7 Functional descriptions This section provides functional description of the TSI module. 48.7.1 Capacitance measurement The electrode pin capacitance measurement uses a dual oscillator approach. The TSI electrode oscillator has its frequency dependable of the external electrode capacitance and of the TSI module configuration. After going to a configurable prescaler, the TSI electrode oscillator signal goes to the input of the module counter.
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Chapter 48 Touch sense input (TSI) 48.7.1.1 TSI electrode oscillator The TSI electrode oscillator circuit is illustrated in the following figure. A configurable constant current source is used to charge and discharge the external electrode capacitance. A buffer hysteresis defines the oscillator delta voltage. The delta voltage defines the margin of high and low voltage which are the reference input of the comparator in different time. Figure 48-33.
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Functional descriptions Felec I 2 * Celec * ΔV Figure 48-35. Equation 1: TSI electrode oscillator frequency Where: I: constant current Celec: electrode capacitance ΔV: Hysteresis delta voltage So by this equation, for example, an electrode with Celec= 20 pF, with a current source of I = 16 µA and ΔV = 600 mV have the following oscillation frequency: Felec 16 µA 2 * 20pF * 600mV 0.67MHz Figure 48-36.
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Chapter 48 Touch sense input (TSI) I: constant current Celec: electrode capacitance ΔV: Hysteresis delta voltage By this equation we have that an electrode with C = 20 pF, with a current source of I = 16 µA and ΔV = 600 mV, PS = 2 and NSCN = 16 have the following sampling time: Tcap_samp 2*2*16*20pF*600mV 48µs 16µA 48.7.1.3 TSI reference oscillator The TSI reference oscillator has the same topology of the TSI electrode oscillator.
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Functional descriptions Using Equation 2 and Equation 1 follows: TSICHnCNT Iref * PS *NSCN * Celec Cref * Ielec Figure 48-39. Equation 5: Capacitance result value In the example where Fref_osc = 10.0MHz and Tcap_samp = 48 µs, TSICHnCNT = 480 48.7.3 Electrode scan unit This session describes the functionality of the electrode scan unit. It is responsible for triggering the start of the active electrode scan.
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Chapter 48 Touch sense input (TSI) Only one electrode pin is functional in the low power mode scan and it’s defined by the bit-field PEN[LPSP]. In low power scan mode the configuration of PEN[PEN] bits are ignored. 48.7.3.2 Scan trigger The scan trigger can be set to periodical scan or software trigger. The bit GENCS[STM] determines the TSI scan trigger mode. If STM = 1 the trigger mode is selected as continuous. If STM = 0, the software trigger mode is selected.
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Functional descriptions 48.7.3.4.1 Active mode periodic scan In active mode periodic scan the scan following clocks can be selected: LPOOSCCLK, MCGIRCLK and OSCERCLK. The bit field SCANC[AMCLKS] selects the TSI clock source for the active mode scan. The scan period is determined by the SCANC[SMOD] value. SMOD is the module of the counter that determines the scan period. The following figure presents the scan sequence performed by the TSI module.
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Chapter 48 Touch sense input (TSI) The GENCS[EOSF] indicates that all active electrode scans are finished and the respective capacitance results are in the TSICHnCNT registers. The GENCS[EOSF] is cleared by writing one to it. 48.7.3.4.4 Over-run interrupt If an electrode scan is in progress and there is a scan trigger the electrode scan unit generates and over-run error by asserting the GENCS[OVRF]. If the TSI error interrupt is active by setting the GENCS[ERIE] bit a interrupt request is asserted.
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Application information 48.7.4.2 Error interrupt The GENCS[EXTERF] is set in the case the capacitance result registers, TSICHnCNT, of a TSI pin is either 0 or 0xFFFF, the two possible extreme values. The EXTERF flag generates a TSI Error Interrupt request if the GENCS[ERIE] bit is set. 48.8 Application information After enable the TSI module for the first time, it is highly recommended a calibration to all the enabled channels by setting proper high and low threshold value for each active channel.
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Chapter 48 Touch sense input (TSI) 48.9.1 Initialization Sequence Freescale TSS library has complete support for TSI, which make the configuration and application much easier. For detailed information on how to work with TSI and TSS together, visit www.freescale.com/touchsensing to get the application notes for details. K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 Freescale Semiconductor, Inc.
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TSI module initialization K20 Sub-Family Reference Manual, Rev. 2, Feb 2012 1214 Freescale Semiconductor, Inc.
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Chapter 49 JTAG Controller (JTAGC) 49.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. 49.1.
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Introduction Power-on reset Test Access Port (TAP) Controller TMS TCK 1-bit Bypass Register 32-bit Device Identification Register TDI TDO Boundary Scan Register TAP Instruction Decoder TAP Instruction Register Figure 49-1. JTAG (IEEE 1149.1) block diagram 49.1.2 Features The JTAGC block is compliant with the IEEE 1149.1-2001 standard, and supports the following features: • IEEE 1149.
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Chapter 49 JTAG Controller (JTAGC) 49.1.3.1 Reset The JTAGC block is placed in reset when either power-on reset is asserted, or the TMS input is held high for enough consecutive rising edges of TCK to sequence the TAP controller state machine into the Test-Logic-Reset state. Holding TMS high for five consecutive rising edges of TCK guarantees entry into the Test-Logic-Reset state regardless of the current TAP controller state. Asserting power-on reset results in asynchronous entry into the reset state.
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External signal description 49.2 External signal description The JTAGC consists of a set of signals that connect to off chip development tools and allow access to test support functions. The JTAGC signals are outlined in the following table and described in the following sections. Table 49-1. JTAG signal properties Name I/O Function Reset State Pull TCK Input Test Clock — Down TDI Input Test Data In — Up TDO Output Test Data Out High Z1 — TMS Input Test Mode Select — Up 1.
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Chapter 49 JTAG Controller (JTAGC) 49.3 Register description This section provides a detailed description of the JTAGC block registers accessible through the TAP interface, including data registers and the instruction register. Individual bit-level descriptions and reset states of each register are included. These registers are not memory-mapped and can only be accessed through the TAP. 49.3.1 Instruction register The JTAGC block uses a 4-bit instruction register as shown in the following figure.
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Register description 49.3.3 Device identification register The device identification (JTAG ID) register, shown in the following figure, allows the revision number, part number, manufacturer, and design center responsible for the design of the part to be determined through the TAP. The device identification register is selected for serial data transfer between TDI and TDO when the IDCODE instruction is active.
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Chapter 49 JTAG Controller (JTAGC) scan register cell, as described in the IEEE 1149.1-2001 standard and discussed in Boundary scan. The size of the boundary scan register and bit ordering is devicedependent and can be found in the device BSDL file. 49.4 Functional description This section explains the JTAGC functional description. 49.4.
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Functional description TEST LOGIC RESET 1 0 1 1 1 SELECT-DR-SCAN RUN-TEST/IDLE SELECT-IR-SCAN 0 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-IR SHIFT-DR 0 0 1 1 1 1 EXIT1-IR EXIT1-DR 0 0 PAUSE-DR PAUSE-IR 0 0 1 0 EXIT2-DR 1 0 EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 The value shown adjacent to each state transition in this figure represents the value of TMS at the time of a rising edge of TCK. Figure 49-4. IEEE 1149.1-2001 TAP controller finite state machine 49.4.3.
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Chapter 49 JTAG Controller (JTAGC) 49.4.3.2 Selecting an IEEE 1149.1-2001 register Access to the JTAGC data registers is achieved by loading the instruction register with any of the JTAGC block instructions while the JTAGC is enabled. Instructions are shifted in via the Select-IR-Scan path and loaded in the Update-IR state. At this point, all data register access is performed via the Select-DR-Scan path.
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Functional description Table 49-3. 4-bit JTAG instructions (continued) Instruction Code[3:0] Instruction Summary ARM JTAG-DP Reserved 1011 This instruction goes the ARM JTAG-DP controller. See the ARM JTAG-DP documentation for more information. CLAMP 1100 Selects bypass register while applying preloaded values to output pins and asserting functional reset ARM JTAG-DP Reserved 1110 This instruction goes the ARM JTAG-DP controller. See the ARM JTAG-DP documentation for more information.
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Chapter 49 JTAG Controller (JTAGC) of the boundary scan register cells on the falling edge of TCK in the Update-DR state. The data is applied to the external output pins by the EXTEST or CLAMP instruction. System operation is not affected. 49.4.4.4 SAMPLE instruction The SAMPLE instruction obtains a sample of the system data and control signals present at the MCU input pins and just before the boundary scan register cells at the output pins.
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Initialization/Application information single bit (the bypass register) while conducting an EXTEST type of instruction through the boundary scan register. CLAMP also asserts the internal system reset for the MCU to force a predictable internal state. 49.4.4.8 BYPASS instruction BYPASS selects the bypass register, creating a single-bit shift register path between TDI and TDO. BYPASS enhances test efficiency by reducing the overall shift path when no test operation of the MCU is required.
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