Information

Section Number Title Page
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................221
12.1.1 Features........................................................................................................................................................221
12.2 Memory map and register definition.............................................................................................................................222
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................223
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................225
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................226
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................229
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................232
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................234
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................235
12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................237
12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................239
12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................241
12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................243
12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................244
12.2.13 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................246
12.2.14 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................247
12.2.15 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................249
12.2.16 Unique Identification Register High (SIM_UIDH).....................................................................................250
12.2.17 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................250
12.2.18 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................251
12.2.19 Unique Identification Register Low (SIM_UIDL)......................................................................................251
12.3 Functional description...................................................................................................................................................251
Chapter 13
Reset Control Module (RCM)
13.1 Introduction...................................................................................................................................................................253
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
10 Freescale Semiconductor, Inc.