Information

• VREF_OUT - V
in1
input
• VDD - V
in2
input
3.7.2.3 External window/sample input
Individual PDB pulse-out signals control each CMP Sample/Window timing.
3.7.3 VREF Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal multiplexing
Module signals
Register
access
VREF
Peripheral bus
controller 0
Other peripherals
Transfers
Figure 3-31. VREF configuration
Table 3-40. Reference links to related information
Topic Related module Reference
Full description VREF VREF
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.3.1 VREF Overview
This device includes a voltage reference (VREF) to supply an accurate 1.2 V voltage
output.
The voltage reference can provide a reference voltage to external peripherals or a
reference to analog peripherals, such as the ADC or CMP.
Connections/Channel Assignment
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
100 Freescale Semiconductor, Inc.