Information

43.5.1 How to manage DSPI queues
The queues are not part of the DSPI, but the DSPI includes features in support of queue
management. Queues are primarily supported in SPI configuration.
1. When DSPI executes last command word from a queue, the EOQ bit in the command
word is set to indicate to the DSPI that this is the last entry in the queue.
2. At the end of the transfer, corresponding to the command word with EOQ set is
sampled, the EOQ flag (EOQF) in the SR is set.
3. The setting of the EOQF flag disables serial transmission and reception of data,
putting the DSPI in the Stopped state. The TXRXS bit is cleared to indicate the
Stopped state.
4. The DMA can continue to fill TX FIFO until it is full or step 5 occurs.
5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA
channel assigned to TX FIFO and RX FIFO. This is done by clearing the
corresponding DMA enable request bits in the DMA Controller.
6. Ensure all received data in RX FIFO has been transferred to memory receive queue
by reading the RXCNT in SR or by checking RFDF in the SR after each read
operation of the POPR.
7. Modify DMA descriptor of TX and RX channels for new queues
8. Flush TX FIFO by writing a 1 to the CLR_TXF bit in the MCR. Flush RX FIFO by
writing a '1' to the CLR_RXF bit in the MCR.
9. Clear transfer count either by setting CTCNT bit in the command word of the first
entry in the new queue or via CPU writing directly to SPI_TCNT field in the TCR.
10. Enable DMA channel by enabling the DMA enable request for the DMA channel
assigned to the DSPI TX FIFO, and RX FIFO by setting the corresponding DMA set
enable request bit.
11. Enable serial transmission and serial reception of data by clearing the EOQF bit.
43.5.2 Switching Master and Slave mode
When changing modes in the DSPI, follow the steps below to guarantee proper operation.
1. Halt the DSPI by setting MCR[HALT].
Initialization/application information
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1002 Freescale Semiconductor, Inc.