Information

2. Clear the transmit and receive FIFOs by writing a 1 to the CLR_TXF and CLR_RXF
bits in MCR.
3. Set the appropriate mode in MCR[MSTR] and enable the DSPI by clearing
MCR[HALT].
43.5.3 Initializing DSPI in Master/Slave Modes
Once the appropriate mode in MCR[MSTR] is configured, the DSPI is enabled by
clearing MCR[HALT]. It should be ensured that DSPI Slave is enabled before enabling
DSPI Master. This ensures the Slave is ready to be communicated with, before Master
initializes communication.
43.5.4 Baud rate settings
The following table shows the baud rate that is generated based on the combination of the
baud rate prescaler PBR and the baud rate scaler BR in the CTARs. The values calculated
assume a 100 MHz system frequency and the double baud rate DBR bit is cleared.
NOTE
The clock frequency mentioned above is given as an example in
this chapter. See the clocking chapter for the frequency used to
drive this module in the device.
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1003