Information

Table 43-60. Delay values
Delay prescaler values
1 3 5 7
Delay scaler values
2 20.0 ns 60.0 ns 100.0 ns 140.0 ns
4 40.0 ns 120.0 ns 200.0 ns 280.0 ns
8 80.0 ns 240.0 ns 400.0 ns 560.0 ns
16 160.0 ns 480.0 ns 800.0 ns 1.1 μs
32 320.0 ns 960.0 ns 1.6 μs 2.2 μs
64 640.0 ns 1.9 μs 3.2 μs 4.5 μs
128 1.3 μs 3.8 μs 6.4 μs 9.0 μs
256 2.6 μs 7.7 μs 12.8 μs 17.9 μs
512 5.1 μs 15.4 μs 25.6 μs 35.8 μs
1024 10.2 μs 30.7 μs 51.2 μs 71.7 μs
2048 20.5 μs 61.4 μs 102.4 μs 143.4 μs
4096 41.0 μs 122.9 μs 204.8 μs 286.7 μs
8192 81.9 μs 245.8 μs 409.6 μs 573.4 μs
16384 163.8 μs 491.5 μs 819.2 μs 1.1 ms
32768 327.7 μs 983.0 μs 1.6 ms 2.3 ms
65536 655.4 μs 2.0 ms 3.3 ms 4.6 ms
43.5.6 Calculation of FIFO pointer addresses
Complete visibility of the TX and RX FIFO contents is available through the FIFO
registers, and valid entries can be identified through a memory-mapped pointer and
counter for each FIFO. The pointer to the first-in entry in each FIFO is memory mapped.
For the TX FIFO the first-in pointer is the Transmit Next Pointer (TXNXTPTR). For the
RX FIFO the first-in pointer is the Pop Next Pointer (POPNXTPTR). The following
figure illustrates the concept of first-in and last-in FIFO entries along with the FIFO
Counter. The TX FIFO is chosen for the illustration, but the concepts carry over to the
RX FIFO. See Transmit First In First Out (TX FIFO) buffering mechanism and Receive
First In First Out (RX FIFO) buffering mechanism for details on the FIFO operation.
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1005