Information

I2Cx_A1 field descriptions (continued)
Field Description
0
Reserved
This read-only field is reserved and always has the value zero.
44.3.2 I2C Frequency Divider register (I2Cx_F)
Addresses: I2C0_F is 4006_6000h base + 1h offset = 4006_6001h
Bit 7 6 5 4 3 2 1 0
Read
MULT ICR
Write
Reset
0 0 0 0 0 0 0 0
I2Cx_F field descriptions
Field Description
7–6
MULT
The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate
the I2C baud rate.
00 mul = 1
01 mul = 2
10 mul = 4
11 Reserved
5–0
ICR
ClockRate
Prescales the bus clock for bit rate selection. This field and the MULT field determine the I2C baud rate,
the SDA hold time, the SCL start hold time, and the SCL stop hold time. For a list of values corresponding
to each ICR setting, see I2C divider and hold values.
The SCL divider multiplied by multiplier factor (mul) determines the I2C baud rate.
I2C baud rate = bus speed (Hz)/(mul × SCL divider)
The SDA hold time is the delay from the falling edge of SCL (I2C clock) to the changing of SDA (I2C
data).
SDA hold time = bus period (s) × mul × SDA hold value
The SCL start hold time is the delay from the falling edge of SDA (I2C data) while SCL is high (start
condition) to the falling edge of SCL (I2C clock).
SCL start hold time = bus period (s) × mul × SCL start hold value
The SCL stop hold time is the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
data) while SCL is high (stop condition).
SCL stop hold time = bus period (s) × mul × SCL stop hold value
For example, if the bus speed is 8 MHz, the following table shows the possible hold time values with
different ICR and MULT selections to achieve an I
2
C baud rate of 100 kbps.
Table continues on the next page...
Chapter 44 Inter-Integrated Circuit (I2C)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1013