Information

I2Cx_F field descriptions (continued)
Field Description
MULT ICR
Hold times (μs)
SDA SCL Start SCL Stop
2h 00h 3.500 3.000 5.500
1h 07h 2.500 4.000 5.250
1h 0Bh 2.250 4.000 5.250
0h 14h 2.125 4.250 5.125
0h 18h 1.125 4.750 5.125
44.3.3 I2C Control Register 1 (I2Cx_C1)
Addresses: I2C0_C1 is 4006_6000h base + 2h offset = 4006_6002h
Bit 7 6 5 4 3 2 1 0
Read
IICEN IICIE MST TX TXAK
0
WUEN DMAEN
Write RSTA
Reset
0 0 0 0 0 0 0 0
I2Cx_C1 field descriptions
Field Description
7
IICEN
I2C Enable
Enables I2C module operation.
0 Disabled
1 Enabled
6
IICIE
I2C Interrupt Enable
Enables I2C interrupt requests.
0 Disabled
1 Enabled
5
MST
Master Mode Select
When the MST bit is changed from a 0 to a 1, a START signal is generated on the bus and master mode
is selected. When this bit changes from a 1 to a 0, a STOP signal is generated and the mode of operation
changes from master to slave.
0 Slave mode
1 Master mode
4
TX
Transmit Mode Select
Table continues on the next page...
Memory map and register descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1014 Freescale Semiconductor, Inc.