Information

44.3.4 I2C Status register (I2Cx_S)
Addresses: I2C0_S is 4006_6000h base + 3h offset = 4006_6003h
Bit 7 6 5 4 3 2 1 0
Read TCF
IAAS
BUSY ARBL
RAM
SRW IICIF RXAK
Write w1c w1c
Reset
1 0 0 0 0 0 0 0
I2Cx_S field descriptions
Field Description
7
TCF
Transfer Complete Flag
This bit sets on the completion of a byte and acknowledge bit transfer. This bit is valid only during or
immediately following a transfer to or from the I2C module. The TCF bit is cleared by reading the I2C data
register in receive mode or by writing to the I2C data register in transmit mode.
0 Transfer in progress
1 Transfer complete
6
IAAS
Addressed As A Slave
This bit is set by one of the following conditions:
• The calling address matches the programmed slave primary address in the A1 register or range
address in the RA register (which must be set to a nonzero value).
• GCAEN is set and a general call is received.
• SIICAEN is set and the calling address matches the second programmed slave address.
• ALERTEN is set and an SMBus alert response address is received
• RMEN is set and an address is received that is within the range between the values of the A1 and
RA registers.
This bit sets before the ACK bit. The CPU must check the SRW bit and set TX/RX accordingly. Writing the
C1 register with any value clears this bit.
0 Not addressed
1 Addressed as a slave
5
BUSY
Bus Busy
Indicates the status of the bus regardless of slave or master mode. This bit is set when a START signal is
detected and cleared when a STOP signal is detected.
0 Bus is idle
1 Bus is busy
4
ARBL
Arbitration Lost
This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by
software, by writing a one to it.
0 Standard bus operation.
1 Loss of arbitration.
3
RAM
Range Address Match
Table continues on the next page...
Memory map and register descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1016 Freescale Semiconductor, Inc.