Information

S C L
S D A
D 0
D a ta B y te
N e w C a llin g A d d r e s s
X X
W r it e
C a llin g A d d r e s s
W r it e
W r ite
S D A
C a llin g A d d re s s R e a d /
X X X D 7 D 6 D 5 D 4 D 3 D 2 D 1A D 6 A D 5A D 7 A D 4
L S B
M S B
1
6
2
5
8
3
4
7
9
1
6
2
5
8
3
4
7
9
L S B
M S B
1
6
2
5
8
3
4
7
9
L S B
M S B
1
6
2
5
8
3
4
7
9
L S B
M S B
A D 6 R / WA D 3 A D 2 A D 1A D 5A D 7 A D 4 A D 6 R / WA D 3 A D 2 A D 1A D 5A D 7 A D 4
R e a d /
R e a d /
R / WA D 3 A D 2 A D 1
SCL
Start Signal
Ack
Bit
No
Ack
Bit
Stop
Signal
Start
Signal
Ack
Bit
Repeated
Start
Signal
No
Ack
Bit
Stop
Signal
Figure 44-26. I2C bus transmission signals
44.4.1.1 START signal
The bus is free when no master device is engaging the bus (both SCL and SDA are high).
When the bus is free, a master may initiate communication by sending a START signal.
A START signal is defined as a high-to-low transition of SDA while SCL is high. This
signal denotes the beginning of a new data transfer—each data transfer might contain
several bytes of data—and brings all slaves out of their idle states.
44.4.1.2 Slave address transmission
Immediately after the START signal, the first byte of a data transfer is the slave address
transmitted by the master. This address is a 7-bit calling address followed by an R/W bit.
The R/W bit tells the slave the desired direction of data transfer.
• 1 = Read transfer: The slave transmits data to the master
• 0 = Write transfer: The master transmits data to the slave
Only the slave with a calling address that matches the one transmitted by the master
responds by sending an acknowledge bit. The slave sends the acknowledge bit by pulling
SDA low at the ninth clock.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1024 Freescale Semiconductor, Inc.