Information

S C L 2
S ta rt C o u n tin g H ig h P e r io d
In te r n a l C o u n te r R e s e t
S C L 1
S C L
D e la y
Figure 44-27. I2C clock synchronization
44.4.1.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfers. A
slave device may hold SCL low after completing a single byte transfer (9 bits). In this
case, it halts the bus clock and forces the master clock into wait states until the slave
releases SCL.
44.4.1.9 Clock stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of
a transfer. After the master drives SCL low, a slave can drive SCL low for the required
period and then release it. If the slave's SCL low period is greater than the master's SCL
low period, the resulting SCL bus signal's low period is stretched. In other words, the
SCL bus signal's low period is increased to be the same length as the slave's SCL low
period.
44.4.1.10 I2C divider and hold values
Table 44-28. I2C divider and hold values
ICR
(hex)
SCL
divider
SDA hold
value
SCL hold
(start)
value
SCL hold
(stop)
value
ICR
(hex)
SCL
divider
(clocks)
SDA hold
(clocks)
SCL hold
(start)
value
SCL hold
(stop)
value
00 20 7 6 11 20 160 17 78 81
01 22 7 7 12 21 192 17 94 97
Table continues on the next page...
Chapter 44 Inter-Integrated Circuit (I2C)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1027