Information

provide manufacturer information, tell the system what its model/part number is, save its
state for a suspend event, report different types of errors, accept control parameters, and
return its status.
44.4.4.1 Timeouts
The T
TIMEOUT,MIN
parameter allows a master or slave to conclude that a defective device
is holding the clock low indefinitely or a master is intentionally trying to drive devices
off the bus. The slave device must release the bus (stop driving the bus and let SCL and
SDA float high) when it detects any single clock held low longer than T
TIMEOUT,MIN
.
Devices that have detected this condition must reset their communication and be able to
receive a new START condition within the timeframe of T
TIMEOUT,MAX
.
SMBus defines a clock low timeout, T
TIMEOUT
, of 35 ms, specifies T
LOW:SEXT
as the
cumulative clock low extend time for a slave device, and specifies T
LOW:MEXT
as the
cumulative clock low extend time for a master device.
44.4.4.1.1 SCL low timeout
If the SCL line is held low by a slave device on the bus, no further communication is
possible. Furthermore, the master cannot force the SCL line high to correct the error
condition. To solve this problem, the SMBus protocol specifies that devices participating
in a transfer must detect any clock cycle held low longer than a timeout value condition.
Devices that have detected the timeout condition must reset the communication. When
the I2C module is an active master, if it detects that SMBCLK low has exceeded the
value of T
TIMEOUT,MIN
, it must generate a stop condition within or after the current data
byte in the transfer process. When the I2C module is a slave, if it detects the
T
TIMEOUT,MIN
condition, it resets its communication and is then able to receive a new
START condition.
44.4.4.1.2 SCL high timeout
When the I2C module has determined that the SMBCLK and SMBDAT signals have
been high for at least T
HIGH:MAX
, it assumes that the bus is idle.
A HIGH timeout occurs after a START condition appears on the bus but before a STOP
condition appears on the bus. Any master detecting this scenario can assume the bus is
free when either of the following occurs:
• SHTF1 rises.
• The BUSY bit is high and SHTF1 is high.
Chapter 44 Inter-Integrated Circuit (I2C)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1031