Information

SCL, SDA
external signals
DFF
Noise
suppress
circuits
SCL, SDA
internal signals
DFF DFF DFF
Figure 44-29. Programmable input glitch filter diagram
44.4.8 Address matching wakeup
When a primary, range, or general call address match occurs when the I2C module is in
slave receive mode, the MCU wakes from a low power mode with no peripheral bus
running. Data sent on the bus that is the same as a target device address might also wake
the target MCU.
After the address matching IAAS bit is set, an interrupt is sent at the end of address
matching to wake the core. The IAAS bit must be cleared after the clock recovery.
NOTE
After the system recovers and is in Run mode, restart the I2C
module if necessary. The SCL line is not held low until the I2C
module resets after address matching.
NOTE
The main purpose of this feature is to wake the MCU from Stop
mode. The main purpose is not communication.
44.4.9 DMA support
If the DMAEN bit is cleared and the IICIE bit is set, an interrupt condition generates an
interrupt request. If the DMAEN bit is set and the IICIE bit is set, an interrupt condition
generates a DMA request instead. DMA requests are generated by the transfer complete
flag (TCF).
If the DMAEN bit is set, the only arbitration lost is to another I2C module (error), and
SCL low timeouts (error) generate CPU interrupts. All other events initiate a DMA
transfer.
NOTE
Before the last byte of master receive mode, TXAK must be set
to send a NACK after the last byte’s transfer. Therefore, the
DMA must be disabled before the last byte’s transfer.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1036 Freescale Semiconductor, Inc.