Information

45.3 Memory map and registers
This section provides a detailed description of all memory and registers.
Accessing reserved addresses within the memory map results in a transfer error. None of
the contents of the implemented addresses are modified as a result of that access.
Only byte accesses are supported.
UART memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_A000 UART Baud Rate Registers: High (UART0_BDH) 8 R/W 00h
45.3.1/
1053
4006_A001 UART Baud Rate Registers: Low (UART0_BDL) 8 R/W 04h
45.3.2/
1054
4006_A002 UART Control Register 1 (UART0_C1) 8 R/W 00h
45.3.3/
1055
4006_A003 UART Control Register 2 (UART0_C2) 8 R/W 00h
45.3.4/
1057
4006_A004 UART Status Register 1 (UART0_S1) 8 R C0h
45.3.5/
1058
4006_A005 UART Status Register 2 (UART0_S2) 8 R/W 00h
45.3.6/
1061
4006_A006 UART Control Register 3 (UART0_C3) 8 R/W 00h
45.3.7/
1063
4006_A007 UART Data Register (UART0_D) 8 R/W 00h
45.3.8/
1065
4006_A008 UART Match Address Registers 1 (UART0_MA1) 8 R/W 00h
45.3.9/
1066
4006_A009 UART Match Address Registers 2 (UART0_MA2) 8 R/W 00h
45.3.10/
1067
4006_A00A UART Control Register 4 (UART0_C4) 8 R/W 00h
45.3.11/
1067
4006_A00B UART Control Register 5 (UART0_C5) 8 R/W 00h
45.3.12/
1068
4006_A00C UART Extended Data Register (UART0_ED) 8 R 00h
45.3.13/
1069
4006_A00D UART Modem Register (UART0_MODEM) 8 R/W 00h
45.3.14/
1070
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1046 Freescale Semiconductor, Inc.