Information

UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_B01B UART 7816 Wait Parameter Register (UART1_WP7816T1) 8 R/W 0Ah
45.3.27/
1083
4006_B01C UART 7816 Wait N Register (UART1_WN7816) 8 R/W 00h
45.3.28/
1084
4006_B01D UART 7816 Wait FD Register (UART1_WF7816) 8 R/W 01h
45.3.29/
1084
4006_B01E UART 7816 Error Threshold Register (UART1_ET7816) 8 R/W 00h
45.3.30/
1085
4006_B01F UART 7816 Transmit Length Register (UART1_TL7816) 8 R/W 00h
45.3.31/
1086
4006_B021 UART CEA709.1-B Control Register 6 (UART1_C6) 8 R/W 00h
45.3.32/
1086
4006_B022
UART CEA709.1-B Packet Cycle Time Counter High
(UART1_PCTH)
8 R/W 00h
45.3.33/
1087
4006_B023
UART CEA709.1-B Packet Cycle Time Counter Low
(UART1_PCTL)
8 R/W 00h
45.3.34/
1088
4006_B024 UART CEA709.1-B Beta1 Timer (UART1_B1T) 8 R/W 00h
45.3.35/
1088
4006_B025
UART CEA709.1-B Secondary Delay Timer High
(UART1_SDTH)
8 R/W 00h
45.3.36/
1089
4006_B026
UART CEA709.1-B Secondary Delay Timer Low
(UART1_SDTL)
8 R/W 00h
45.3.37/
1089
4006_B027 UART CEA709.1-B Preamble (UART1_PRE) 8 R/W 00h
45.3.38/
1090
4006_B028 UART CEA709.1-B Transmit Packet Length (UART1_TPL) 8 R/W 00h
45.3.39/
1090
4006_B029 UART CEA709.1-B Interrupt Enable Register (UART1_IE) 8 R/W 00h
45.3.40/
1091
4006_B02A UART CEA709.1-B WBASE (UART1_WB) 8 R/W 00h
45.3.41/
1092
4006_B02B UART CEA709.1-B Status Register (UART1_S3) 8 R/W 00h
45.3.42/
1092
4006_B02C UART CEA709.1-B Status Register (UART1_S4) 8 R/W 00h
45.3.43/
1094
4006_B02D UART CEA709.1-B Received Packet Length (UART1_RPL) 8 R 00h
45.3.44/
1095
4006_B02E
UART CEA709.1-B Received Preamble Length
(UART1_RPREL)
8 R 00h
45.3.45/
1095
4006_B02F UART CEA709.1-B Collision Pulse Width (UART1_CPW) 8 R/W 00h
45.3.46/
1096
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1050 Freescale Semiconductor, Inc.