Information

UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_C028 UART CEA709.1-B Transmit Packet Length (UART2_TPL) 8 R/W 00h
45.3.39/
1090
4006_C029 UART CEA709.1-B Interrupt Enable Register (UART2_IE) 8 R/W 00h
45.3.40/
1091
4006_C02A UART CEA709.1-B WBASE (UART2_WB) 8 R/W 00h
45.3.41/
1092
4006_C02B UART CEA709.1-B Status Register (UART2_S3) 8 R/W 00h
45.3.42/
1092
4006_C02C UART CEA709.1-B Status Register (UART2_S4) 8 R/W 00h
45.3.43/
1094
4006_C02D UART CEA709.1-B Received Packet Length (UART2_RPL) 8 R 00h
45.3.44/
1095
4006_C02E
UART CEA709.1-B Received Preamble Length
(UART2_RPREL)
8 R 00h
45.3.45/
1095
4006_C02F UART CEA709.1-B Collision Pulse Width (UART2_CPW) 8 R/W 00h
45.3.46/
1096
4006_C030
UART CEA709.1-B Receive Indeterminate Time
(UART2_RIDT)
8 R/W 00h
45.3.47/
1096
4006_C031
UART CEA709.1-B Transmit Indeterminate Time
(UART2_TIDT)
8 R/W 00h
45.3.48/
1097
45.3.1 UART Baud Rate Registers: High (UARTx_BDH)
This register, along with the BDL register, controls the prescale divisor for UART baud
rate generation. To update the 13-bit baud rate setting (SBR[12:0]), first write to BDH to
buffer the high half of the new value and then write to BDL. The working value in BDH
does not change until BDL is written.
BDL is reset to a nonzero value, but after reset, the baud rate generator remains disabled
until the first time the receiver or transmitter is enabled, that is, when C2[RE] or C2[TE]
is set.
Addresses: UART0_BDH is 4006_A000h base + 0h offset = 4006_A000h
UART1_BDH is 4006_B000h base + 0h offset = 4006_B000h
UART2_BDH is 4006_C000h base + 0h offset = 4006_C000h
Bit 7 6 5 4 3 2 1 0
Read
LBKDIE RXEDGIE
0
SBR
Write
Reset
0 0 0 0 0 0 0 0
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1053