Information

UARTx_C2 field descriptions (continued)
Field Description
0 Transmitter off.
1 Transmitter on.
2
RE
Receiver Enable
Enables the UART receiver.
0 Receiver off.
1 Receiver on.
1
RWU
Receiver Wakeup Control
This field can be set to place the UART receiver in a standby state. RWU automatically clears when an
RWU event occurs, that is, an IDLE event when C1[WAKE] is clear or an address match when C1[WAKE]
is set. This field must be cleared when C7816[ISO_7816E] is set.
NOTE: RWU must be set only with C1[WAKE] = 0 (wakeup on idle) if the channel is currently not idle.
This can be determined by S2[RAF]. If the flag is set to wake up an IDLE event and the channel
is already idle, it is possible that the UART will discard data. This is because the data must be
received or a LIN break detected after an IDLE is detected before IDLE is allowed to reasserted.
0 Normal operation.
1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware
wakes the receiver by automatically clearing RWU.
0
SBK
Send Break
Toggling SBK sends one break character from the following: See for the number of logic 0s for the
different configurations. Toggling implies clearing the SBK field before the break character has finished
transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10, 11,
or 12 bits, or 13 or 14 bits).
• 10, 11, or 12 logic 0s if S2[BRK13] is cleared
• 13 or 14 logic 0s if S2[BRK13] is set.
Transmitting break charactersThis field must be cleared when C7816[ISO_7816E] is set.
0 Normal transmitter operation.
1 Queue break characters to be sent.
45.3.5 UART Status Register 1 (UARTx_S1)
The S1 register provides inputs to the MCU for generation of UART interrupts or DMA
requests. This register can also be polled by the MCU to check the status of its fields. To
clear a flag, the status register should be read followed by a read or write to D register,
depending on the interrupt flag type. Other instructions can be executed between the two
steps as long the handling of I/O is not compromised, but the order of operations is
important for flag clearing. When a flag is configured to trigger a DMA request, assertion
of the associated DMA done signal from the DMA controller clears the flag.
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1058 Freescale Semiconductor, Inc.