Information

UARTx_S1 field descriptions (continued)
Field Description
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
5
RDRF
Receive Data Register Full Flag
RDRF is set when the number of datawords in the receive buffer is equal to or more than the number
indicated by RWFIFO[RXWATER]. A dataword that is in the process of being received is not included in
the count. RDRF is prevented from setting while S2[LBKDE] is set. Additionally, when S2[LBKDE] is set,
the received datawords are stored in the receive buffer but over-write each other. To clear RDRF, read S1
when RDRF is set and then read D. For more efficient interrupt and DMA operation, read all data except
the final value from the buffer, using D/C3[T8]/ED. Then read S1 and the final data value, resulting in the
clearing of the RDRF flag. Even if RDRF is set, data will continue to be received until an overrun condition
occurs.
0 The number of datawords in the receive buffer is less than the number indicated by RXWATER.
1 The number of datawords in the receive buffer is equal to or greater than the number indicated by
RXWATER at some point in time since this flag was last cleared.
4
IDLE
Idle Line Flag
After the IDLE flag is cleared, a frame must be received (although not necessarily stored in the data
buffer, for example if C2[RWU] is set), or a LIN break character must set the S2[LBKDIF] flag before an
idle condition can set the IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
IDLE is set when either of the following appear on the receiver input:
• 10 consecutive logic 1s if C1[M] = 0
• 11 consecutive logic 1s if C1[M] = 1 and C4[M10] = 0
• 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1
Idle detection is not supported when7816Eor EN709is set/enabled and hence this flag is ignored.
NOTE: When RWU is set and WAKE is cleared, an idle line condition sets the IDLE flag if RWUID is set,
else the IDLE flag does not become set.
0 Receiver input is either active now or has never become active since the IDLE flag was last cleared.
1 Receiver input has become idle or the flag has not been cleared since it last asserted.
3
OR
Receiver Overrun Flag
OR is set when software fails to prevent the receive data register from overflowing with data. The OR bit
is set immediately after the stop bit has been completely received for the dataword that overflows the
buffer and all the other error flags (FE, NF, and PF) are prevented from setting. The data in the shift
register is lost, but the data already in the UART data registers is not affected. If the OR flag is set, no
data is stored in the data buffer even if sufficient room exists. Additionally, while the OR flag is set, the
RDRF and IDLE flags are blocked from asserting, that is, transition from an inactive to an active state. To
clear OR, read S1 when OR is set and then read D. If LBKDE is enabled and a LIN Break is detected, the
OR field asserts if S2[LBKDIF] is not cleared before the next data character is received.See for more
details regarding the operation of the OR bit. Overrun (OR) flag implicationsIn 7816 mode, it is possible to
configure a NACK to be returned by programing C7816[ONACK].
0 No overrun has occurred since the last time the flag was cleared.
1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
2
NF
Noise Flag
NF is set when the UART detects noise on the receiver input. NF does not become set in the case of an
overrun or while the LIN break detect feature is enabled (S2[LBKDE] = 1). When NF is set, it indicates
only that a dataword has been received with noise since the last time it was cleared. There is no
guarantee that the first dataword read from the receive buffer has noise or that there is only one dataword
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1060 Freescale Semiconductor, Inc.