Information

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 32-Bit 50 MHz I/O number 40

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UARTx_S2 field descriptions (continued)

Field Description

BRK13

Break Transmit Character Length

Determines whether the transmit break character is 10, 11, or 12 bits long, or 13 or 14 bits long. See for

the length of the break character for the different configurations. The detection of a framing error is not

affected by this field. Transmitting break characters

0 Break character is 10, 11, or 12 bits long.

1 Break character is 13 or 14 bits long.

LBKDE

LIN Break Detection Enable

Selects a longer break character detection length. While LBKDE is set, S1[RDRF], S1[NF], S1[FE], and

S1[PF] are prevented from setting. When LBKDE is set, see . Overrun operationLBKDE must be cleared

when C7816[ISO7816E] is set.

0 Break character is detected at one of the following lengths:

• 10 bit times if C1[M] = 0

• 11 bit times if C1[M] = 1 and C4[M10] = 0

• 12 bit times if C1[M] = 1, C4[M10] = 1, and S1[PE] = 1

1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.

RAF

Receiver Active Flag

RAF is set when the UART receiver detects a logic 0 during the RT1 time period of the start bit search.

RAF is cleared when the receiver detects an idle character when C7816[ISO7816E] is cleared/disabled.

When C7816[ISO7816E] is enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the

C7816[TTYPE] = 1 expires.

NOTE: In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible to configure the guard

time to 12. However, if a NACK is required to be transmitted, the data transfer actually takes 13

ETU with the 13th ETU slot being a inactive buffer. Therefore, in this situation, the RAF may

deassert one ETU prior to actually being inactive.

0 UART receiver idle/inactive waiting for a start bit.

1 UART receiver active, RxD input not idle.

45.3.7 UART Control Register 3 (UARTx_C3)

Writing R8 does not have any effect. TXDIR and TXINV can be changed only between

transmit and receive packets.

Addresses: UART0_C3 is 4006_A000h base + 6h offset = 4006_A006h

UART1_C3 is 4006_B000h base + 6h offset = 4006_B006h

UART2_C3 is 4006_C000h base + 6h offset = 4006_C006h

Bit 7 6 5 4 3 2 1 0

Read R8

T8 TXDIR TXINV ORIE NEIE FEIE PEIE

Write

Reset

0 0 0 0 0 0 0 0

Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

Freescale Semiconductor, Inc. 1063