Information

UARTx_C3 field descriptions (continued)
Field Description
Enables the framing error flag, S1[FE], to generate interrupt requests.
0 FE interrupt requests are disabled.
1 FE interrupt requests are enabled.
0
PEIE
Parity Error Interrupt Enable
Enables the parity error flag, S1[PF], to generate interrupt requests.
0 PF interrupt requests are disabled.
1 PF interrupt requests are enabled.
45.3.8 UART Data Register (UARTx_D)
This register is actually two separate registers. Reads return the contents of the read-only
receive data register and writes go to the write-only transmit data register.
NOTE
• In 8-bit or 9-bit data format, only UART data register (D)
needs to be accessed to clear the S1[RDRF] bit (assuming
receiver buffer level is less than RWFIFO[RXWATER]).
The C3 register needs to be read, prior to the D register,
only if the ninth bit of data needs to be captured. Similarly,
the ED register needs to be read, prior to the D register,
only if the additional flag data for the dataword needs to be
captured.
• In the normal 8-bit mode (M bit cleared) if the parity is
enabled, you get seven data bits and one parity bit. That
one parity bit is loaded into the D register. So, for the data
bits, mask off the parity bit from the value you read out of
this register.
• When transmitting in 9-bit data format and using 8-bit
write instructions, write first to transmit bit 8 in UART
control register 3 (C3[T8]), then D. A write to C3[T8]
stores the data in a temporary register. If D register is
written first, and then the new data on data bus is stored in
D, the temporary value written by the last write to C3[T8]
gets stored in the C3[T8] register.
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1065