Information

45.3.10 UART Match Address Registers 2 (UARTx_MA2)
These registers can be read and written at anytime. The MA1 and MA2 registers are
compared to input data addresses when the most significant bit is set and the associated
C4[MAEN] field is set. If a match occurs, the following data is transferred to the data
register. If a match fails, the following data is discarded.
Addresses: UART0_MA2 is 4006_A000h base + 9h offset = 4006_A009h
UART1_MA2 is 4006_B000h base + 9h offset = 4006_B009h
UART2_MA2 is 4006_C000h base + 9h offset = 4006_C009h
Bit 7 6 5 4 3 2 1 0
Read
MA
Write
Reset
0 0 0 0 0 0 0 0
UARTx_MA2 field descriptions
Field Description
7–0
MA
Match Address
45.3.11 UART Control Register 4 (UARTx_C4)
Addresses: UART0_C4 is 4006_A000h base + Ah offset = 4006_A00Ah
UART1_C4 is 4006_B000h base + Ah offset = 4006_B00Ah
UART2_C4 is 4006_C000h base + Ah offset = 4006_C00Ah
Bit 7 6 5 4 3 2 1 0
Read
MAEN1 MAEN2 M10 BRFA
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C4 field descriptions
Field Description
7
MAEN1
Match Address Mode Enable 1
See Match address operation for more information.
0 All data received is transferred to the data buffer if MAEN2 is cleared.
1 All data received with the most significant bit cleared, is discarded. All data received with the most
significant bit set, is compared with contents of MA1 register. If no match occurs, the data is
discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when
C7816[ISO7816E] is set/enabled.
6
MAEN2
Match Address Mode Enable 2
Table continues on the next page...
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1067