Information

UARTx_CFIFO field descriptions (continued)
Field Description
0
RXUFE
Receive FIFO Underflow Interrupt Enable
When this field is set, the RXUF flag generates an interrupt to the host.
0 RXUF flag does not generate an interrupt to the host.
1 RXUF flag generates an interrupt to the host.
45.3.18 UART FIFO Status Register (UARTx_SFIFO)
This register provides status information regarding the transmit and receiver buffers/
FIFOs, including interrupt information. This register may be written to or read at any
time.
Addresses: UART0_SFIFO is 4006_A000h base + 12h offset = 4006_A012h
UART1_SFIFO is 4006_B000h base + 12h offset = 4006_B012h
UART2_SFIFO is 4006_C000h base + 12h offset = 4006_C012h
Bit 7 6 5 4 3 2 1 0
Read TXEMPT RXEMPT 0
RXOF TXOF RXUF
Write
Reset
1 1 0 0 0 0 0 0
UARTx_SFIFO field descriptions
Field Description
7
TXEMPT
Transmit Buffer/FIFO Empty
Asserts when there is no data in the Transmit FIFO/buffer. This field does not take into account data that
is in the transmit shift register.
0 Transmit buffer is not empty.
1 Transmit buffer is empty.
6
RXEMPT
Receive Buffer/FIFO Empty
Asserts when there is no data in the receive FIFO/Buffer. This field does not take into account data that is
in the receive shift register.
0 Receive buffer is not empty.
1 Receive buffer is empty.
5–3
Reserved
This read-only field is reserved and always has the value zero.
2
RXOF
Receiver Buffer Overflow Flag
Indicates that more data has been written to the receive buffer than it can hold. This field will assert
regardless of the value of CFIFO[RXOFE]. However, an interrupt will be issued to the host only if
CFIFO[RXOFE] is set. This flag is cleared by writing a 1.
Table continues on the next page...
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1075