Information

45.3.20 UART FIFO Transmit Count (UARTx_TCFIFO)
This is a read only register that indicates how many datawords are currently in the
transmit buffer/FIFO. It may be read at any time.
Addresses: UART0_TCFIFO is 4006_A000h base + 14h offset = 4006_A014h
UART1_TCFIFO is 4006_B000h base + 14h offset = 4006_B014h
UART2_TCFIFO is 4006_C000h base + 14h offset = 4006_C014h
Bit 7 6 5 4 3 2 1 0
Read TXCOUNT
Write
Reset
0 0 0 0 0 0 0 0
UARTx_TCFIFO field descriptions
Field Description
7–0
TXCOUNT
Transmit Counter
The value in this register indicates the number of datawords that are in the transmit FIFO/buffer. If a
dataword is being transmitted, that is, in the transmit shift register, it is not included in the count. This
value may be used in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the
transmit FIFO/buffer.
45.3.21 UART FIFO Receive Watermark (UARTx_RWFIFO)
This register provides the ability to set a programmable threshold for notification of the
need to remove data from the receiver FIFO/buffer. This register may be read at any time
but must be written only when C2[RE] is not asserted. Changing the value in this register
will not clear S1[RDRF].
Addresses: UART0_RWFIFO is 4006_A000h base + 15h offset = 4006_A015h
UART1_RWFIFO is 4006_B000h base + 15h offset = 4006_B015h
UART2_RWFIFO is 4006_C000h base + 15h offset = 4006_C015h
Bit 7 6 5 4 3 2 1 0
Read
RXWATER
Write
Reset
0 0 0 0 0 0 0 1
UARTx_RWFIFO field descriptions
Field Description
7–0
RXWATER
Receive Watermark
When the number of datawords in the receive FIFO/buffer is equal to or greater than the value in this
register field, an interrupt via S1[RDRF] or a DMA request via C5[RDMAS] is generated as determined by
C5[RDMAS] and C2[RIE]. For proper operation, the value in RXWATER must be set to be less than the
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1077