Information

45.3.34 UART CEA709.1-B Packet Cycle Time Counter Low
(UARTx_PCTL)
Addresses: UART0_PCTL is 4006_A000h base + 23h offset = 4006_A023h
UART1_PCTL is 4006_B000h base + 23h offset = 4006_B023h
UART2_PCTL is 4006_C000h base + 23h offset = 4006_C023h
Bit 7 6 5 4 3 2 1 0
Read
PCTL
Write
Reset
0 0 0 0 0 0 0 0
UARTx_PCTL field descriptions
Field Description
7–0
PCTL
Packet Cycle Time Counter Low
Indicates the least significant byte of maximum period after the line code violation for which the bus could
remain idle without decrementing back log count. If the time elapsed after line code violation is greater
than packet cycle time, then packet cycle timer expired interrupt is generated. It is measured in terms of
bit times, that is, the time it takes for a single bit or one Differential Manchester symbol to be transmitted.
This is medium dependent and therefore does not usually require adjustment and is programmed only
once.
45.3.35 UART CEA709.1-B Beta1 Timer (UARTx_B1T)
Addresses: UART0_B1T is 4006_A000h base + 24h offset = 4006_A024h
UART1_B1T is 4006_B000h base + 24h offset = 4006_B024h
UART2_B1T is 4006_C000h base + 24h offset = 4006_C024h
Bit 7 6 5 4 3 2 1 0
Read
B1T
Write
Reset
0 0 0 0 0 0 0 0
UARTx_B1T field descriptions
Field Description
7–0
B1T
Beta1 Timer
Beta1 delay is a value that is system dependent and usually does not require adjustment. It is
programmed only once and measured in bit times.
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1088 Freescale Semiconductor, Inc.