Information

45.3.38 UART CEA709.1-B Preamble (UARTx_PRE)
Addresses: UART0_PRE is 4006_A000h base + 27h offset = 4006_A027h
UART1_PRE is 4006_B000h base + 27h offset = 4006_B027h
UART2_PRE is 4006_C000h base + 27h offset = 4006_C027h
Bit 7 6 5 4 3 2 1 0
Read
PREAMBLE
Write
Reset
0 0 0 0 0 0 0 0
UARTx_PRE field descriptions
Field Description
7–0
PREAMBLE
CEA709.1-B Preamble Register
The number of bit-sync characters that occur prior to the byte-sync character when preamble is
transmitted.
NOTE: The minimum preamble length supported by twisted pair wire is four bit-sync fields.
45.3.39 UART CEA709.1-B Transmit Packet Length (UARTx_TPL)
Addresses: UART0_TPL is 4006_A000h base + 28h offset = 4006_A028h
UART1_TPL is 4006_B000h base + 28h offset = 4006_B028h
UART2_TPL is 4006_C000h base + 28h offset = 4006_C028h
Bit 7 6 5 4 3 2 1 0
Read
TPL
Write
Reset
0 0 0 0 0 0 0 0
UARTx_TPL field descriptions
Field Description
7–0
TPL
Transmit Packet Length Register
Length of the data packet in bytes that is transmitted by CEA709.1-B transmitter. This includes the CRC
packet as well.
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1090 Freescale Semiconductor, Inc.