Information

UARTx_S3 field descriptions (continued)
Field Description
line code violation is transmitted on TX line immediately after the current byte or preamble transmission is
finished, without waiting for completion of transmit packet length. If the transmission fail flag is asserted,
C6[TX709] is cleared. This flag is cleared by writing 1.
0 Transmission continues normally.
1 Transmission has failed.
45.3.43 UART CEA709.1-B Status Register (UARTx_S4)
Addresses: UART0_S4 is 4006_A000h base + 2Ch offset = 4006_A02Ch
UART1_S4 is 4006_B000h base + 2Ch offset = 4006_B02Ch
UART2_S4 is 4006_C000h base + 2Ch offset = 4006_C02Ch
Bit 7 6 5 4 3 2 1 0
Read 0 INITF
CDET ILCV FE
Write
Reset
0 0 0 0 0 0 0 0
UARTx_S4 field descriptions
Field Description
7–5
Reserved
This read-only field is reserved and always has the value zero.
4
INITF
Initial Synchronization Fail Flag
Indicates that the initial synchronization has failed and the packet cycle time has expired after enabling
EN709 register. This flag is cleared if EN709 is cleared.
0 Initial synchronization has not failed.
1 Initial synchronization has failed.
3–2
CDET
CDET
Indicates when the collision occurs during transmission. This flag is cleared by writing 2'b11. If the
collision flag is not cleared by software and a valid collision pulse is detected during some other phase of
transmission, then collision flag continues to indicate the previous value.
00 No collision.
01 Collision occurred during preamble.
10 Collision occurred during data.
11 Collision occurred during line code violation.
1
ILCV
Improper Line Code Violation
Indicates that line code violation received is not proper. This flag is cleared by writing 1.
0 Line code violation received is proper.
1 Line code violation received is improper, that is, less than three bit periods.
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1094 Freescale Semiconductor, Inc.