Information

45.4.1.2 Packet cycle and delay calculations
1
2
1
2
w
Randomizing
w i ndow
Priority
slots
Packet
Packet
Figure 45-195. CEA709.1-B packet cycle
Predictive p-persistent CSMA is a technique for collision avoidance that randomizes
channel access using knowledge of predicted load. It manages software using data and
events reported by the hardware.
Beta1 delay is a value set by the software. It is generally a fixed value that is system
dependent and hence does not usually require adjustment. It is measured in bit times, that
is, the time that it takes for a single bit to be transmitted or one differential Manchester
symbol. Beta1 is defined by CEA/EIA-709 specification as:
Beta1 > 1 bit time + (2 × T
aup
+ T
aum
)
Where T
aup
is the physical propagation delay defined by the media length.
T
aum
is the detection and turn around-delay within the MAC sublayer; this is the period
from the time the idle channel condition is detected, to the point when the first output
transition appears on the output. On media where there is a carrier, this time must include
the time between turning on the carrier, and it being asserted as a valid carrier on the
medium.
The secondary delay timer is a value that is set by software. This is generally a variable
value that must be set for each data message to be transmitted. It is measured in bit times,
that is, the time that it takes for a single bit to be transmitted or one differential
Manchester symbol. This value must be between 0 and (BL × Wbase) + (ProritySlots -1),
Beta2 timeslots. A value of zero indicates that the queued packet for transmit is to be sent
immediately upon expiration of the beta1 timer. According to the CEA/EIA-709
specification:
• BL is back log
• Wbase is 16 beta2 timeslots
• A priorityslot is the same amount of time as a beta2 timeslot
• Beta2 > 2 × T
aup
+ T
aum
Priority slots are handled completely by software. When calculating the secondary delay
timer value, the software must take into account any priority slot that is included in the
design of the system.
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1099