Information

3.8.4.2 LPTMR pulse counter input options
The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode.
The following table shows the chip-specific input assignments for this bitfield.
LPTMR_CSR[TPS] Pulse counter input number Chip input
00 0 CMP0 output
01 1 LPTMR_ALT1 pin
10 2 LPTMR_ALT2 pin
11 3 Reserved
3.8.5 CMT Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal multiplexing
Module signals
Register
access
CMT
Peripheral bus
controller 0
Figure 3-38. CMT configuration
Table 3-50. Reference links to related information
Topic Related module Reference
Full description Carrier modulator
transmitter (CMT)
CMT
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.8.5.1 Instantiation Information
This device contains one CMT module.
Timers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
110 Freescale Semiconductor, Inc.