Information

Each node must maintain an estimation of the current channel backlog. Backlog
calculation is managed by the layer two software. Initially, the backlog is set to one. The
backlog is incremented on transmission by a value indicated in the frames backlog
increment field.
The backlog decrements under the following conditions:
• On waiting to transmit: If Wbase randomizing slots go by without channel activity.
• On receive: If a packet is received with a backlog increment of 0.
• On transmit: If a packet is transmitted with a backlog increment of 0.
• On idle: If a packet cycle time expires without channel activity.
The following actions need to be completed when a frame is received to prepare an
outgoing message for transmission after the channel becomes idle:
• CRC of incoming message needs to be verified by software.
• If the CRC is good, the BL is recalculated, otherwise BL remains the same.
• Transmit delay (secondary delay timer) is calculated and supplied to UART.
45.4.1.3 Clock resynchronization
The UART is transmitting on time base source. Therefore, all receivers keep
synchronizing with the node that is transmitting and no clock resynchronization occurs in
transmitting.
When the UART is receiving or waiting to transmit, clock resynchronization is vital.
Because long streams of data are possible (up to 229 bytes + headers), there exists
significant potential for nodes to wander regarding time reference over the course of the
message. Therefore, Differential Manchester Encoding (DME) is used. While DME
requires twice the bandwidth of non-return to zero (NRZ) encoding schemes, it has the
benefit of a guaranteed transition at the start of each bit transmitter. A transition
occurring at the middle of the bit is encoded as a logic 0 or the lack of a transition at the
middle of the bit time is encoded as a logic 1. By detecting the transition at the start of a
bit period, the receiver is able to be resynthesized to the transmitter every bit period.
Resynchronization can occur only after the node is already synchronized with the system.
Additionally, for resynchronization to be effective, some basic assumptions regarding the
system must be made:
1. Only a single channel sample may be in error (noise) over the entire bit (16 samples)
period.
2. While a node is drifted from the system time base, with the resynchronization, the
node is never shifted by more than 2 data samples in a given bit period.
3. If multiple noise events have occurred, no action is taken.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1100 Freescale Semiconductor, Inc.