Information
Sample Values (15,16,1,2,3) Action / Event
DDSDD It is most likely that sample 1 is noise. Therefore, the time
base is sped up by two. Sample 15 becomes sample 1,
sample 16 becomes sample 2, sample 1 becomes sample 3,
sample 2 becomes sample 4, sample 3 becomes sample 5,
and the next sample taken is sample 6.
DDDSS In this case multiple errors occurred along with time shift.
Therefore, no adjustment to time base is made.
DDDSD It is most likely that sample 2 is noise. Therefore, the time
base is sped up by two. Sample 15 becomes sample 1,
sample 16 becomes sample 2, sample 1 becomes sample 3,
sample 2 becomes sample 4, sample 3 becomes sample 5,
and the next sample taken is sample 6.
DDDDS It is most likely that sample 3 is noise. Therefore, the time
base is sped up by two. Sample 15 becomes sample 1,
sample 16 becomes sample 2, sample 1 becomes sample 3,
sample 2 becomes sample 4, sample 3 becomes sample 5,
and the next sample taken is sample 6.
DDDDD Either samples 15 and 16 are noise or the time base has
shifted. Therefore, the time base is sped up by two. Sample
15 becomes sample 1, sample 16 becomes sample 2,
sample 1 becomes sample 3, sample 2 becomes sample 4,
sample 3 becomes sample 5, and the next sample taken is
sample 6.
45.4.1.4 Data sampling
The receiver samples the unsynchronized receiver input signal at the RT clock rate. The
RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud
rate mismatch, the RT clock is resynchronized after every bit.
To locate the start of preamble, data recovery logic does an asynchronous search for a
logic 0 preceded by three logic 1s or logic 1 preceded by three logic 0s. When the falling
edge or rising edge of a possible preamble bit occurs, the RT clock begins to count to 16.
RESET RT CLOCK
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT8
RT7
RT6
RT11
RT10
RT9
RT15
RT14
RT13
RT12
RT16
RT1
RT2
RT3
RT4
SAMPLES
RT CLOCK
RT CLOCK COUNT
PREAMBLE
Rx pin input
PREAMBLE
QUALIFICATION
PREAMBLE
1 111111 1 0 0 0
VERIFICATION
0
Figure 45-196. Receiver data sampling
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1103