Information

To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5,
and RT7. The following table summarizes the results of the preamble verification
samples.
Table 45-200. Preamble/ Data bit verification
RT3, RT5, and RT7 samples Preamble verification
000 Yes
001 Yes
010 Yes
011 No
100 Yes
101 No
110 No
111 No
If preamble verification is not successful, the RT clock is reset and a new search for a
preamble begins.
To determine the value of a data bit, recovery logic takes samples at RT11, RT12, and
RT13. The following table summarizes the results of the data bit samples. If the majority
of RT11, RT12, and RT13 samples is the same as the majority of RT3, RT5, and RT7
samples, then the data bit detected is 1, else the data bit detected is 0.
Table 45-201. Data bit recovery
RT11, RT12, and RT13 samples Data bit determination
000 0
001 0
010 0
011 1
100 0
101 1
110 1
111 1
To signify the end of a data packet, the transmitter causes a line-code violation to occur,
that is, the transmitter remains transitionless for at least 3-bit periods after the final clock
transition, excluding the final data transition, if it exists. The receiver detects this
violation. For the purpose of detecting a line-code violation, the receiver monitors the
channel to locate a series of five or six back-to-back half bit periods.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1104 Freescale Semiconductor, Inc.