Information

45.4.1.5 Initial clock synchronization
When operating with EN709 set, there are various times when initial clock
synchronization is required. When the UART has just been enabled, there is clearly no
system clock reference. Additionally, if a channel has remained idle for a significant
period of time, such as the arbitration time between packets, substantial clock drift may
have occurred in the system between nodes. This is because there have been meaningful
clock transitions on the channel to keep nodes synchronized. After these events, the clock
may require significant synchronization adjustment; this event is referred to as initial
clock synchronization.
There are three situations that may occur when a node attempts to obtain initial clock
synchronization.
1. The node enters the system while a data packet is being actively transmitted.
2. The node enters the system while there is no data packet being actively transmitted
on the system.
3. The node is already in the system and initial clock synchronization is required due to
the end of a packet.
For case 1 and 2, the UART implements the following procedure:
1. The UART attempts to identify a valid edge to synchronize with.
2. While the UART attempts to locate a valid edge, it also tries to identify a line code
violation of 8 back-to-back half bit time samples rather than the 6. It is not required
to finish the current bit because the clock is not synchronized. If the required line-
code violation is detected, the beta1 delay timer will start and the UART will transit
to case 3.
3. If an edge is determined to be valid, that node will consider itself synchronized but
will not start receiving, or attempt to send data, until a line code violation has been
identified.
4. If no valid edge is determined and meanwhile the packet cycle timer expires, it is
indicated to the processor that initial synchronization has failed and the processor can
choose to transmit the data.
For case 3, it implements the following procedure:
1. Beta1 delay and secondary delay times increment as appropriate, that is Beta1 delay
expires before the secondary delay timer starts.
2. While the timers are counting, the UART attempts to identify a valid edge.
3. If a valid edge is identified before the time expires, and data is queued to be
transmitted, the transmission failure asserts and the clock is considered synchronized.
The incoming data packet is received.
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1105