Information

45.4.3 Receiver
M
PE
PT
RE
VARIABLE 12-BIT RECEIVE
STOP START
RECEIVE
WAKEUP
DATA BUFFER
INTERNAL BUS
MODULE
SBR12:0
BAUDRATE
CLOCK
RAF
LOGIC
SHIFT DIRECTION
ACTIVE EDGE
DETECT
LBKDE
BRFA4:0
MSBF
GENERATOR
SHIFT REGISTER
M10
RXINV
IRQ / DMA
LOGIC
DMA Requests
IRQ Requests
PARITY
LOGIC
CONTROL
RxD
RxD
LOOPS
RSRC
From Transmitter
RECEIVER
SOURCE
CONTROL
7816 LOGIC
To TxD
INFRARED LOGIC
Figure 45-200. UART receiver block diagram
45.4.3.1 Receiver character length
The UART receiver can accommodate 8-, 9-, or 10-bit data characters. The states of
C1[M], C1[PE], and C4[M10] determine the length of data characters. When receiving 9
or 10-bit data, C3[R8] is the ninth bit (bit 8).
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1114 Freescale Semiconductor, Inc.