Information

45.4.3.2 Receiver bit ordering

When S2[MSBF] is set, the receiver operates such that the first bit received after the start

bit is the MSB of the dataword. Similarly, the bit received immediately preceding the

parity bit, or the stop bit if parity is not enabled, is treated as the LSB for the dataword.

All necessary bit ordering is handled automatically by the module. Therefore, the format

of the data read from receive data buffer is completely independent of S2[MSBF].

45.4.3.3 Character reception

During UART reception, the receive shift register shifts a frame in from the

unsynchronized receiver input signal. After a complete frame shifts into the receive shift

the noise and parity error flags that are calculated during the receive process are also

captured in the UART receive buffer. The receive data buffer is accessible via the D and

C3[T8] registers. Additional received information flags regarding the receive dataword

can be read in ED register. S1[RDRF] is set if the number of resulting datawords in the

receive buffer is equal to or greater than the number indicated by RWFIFO[RXWATER].

If the C2[RIE] is also set, RDRF generates an RDRF interrupt request. Alternatively, by

programming C5[RDMAS] correctly, a DMA request can be generated.

When C7816[ISO_7816E] is set/enabled and C7816[TTYPE] = 0, character reception

operates slightly differently. Upon receipt of the parity bit, the validity of the parity bit is

checked. If C7816[ANACK] is set and the parity check fails, or if INIT and the received

character is not a valid initial character, then a NACK is sent by the receiver. If the

number of consecutive receive errors exceeds the threshold set by

ET7816[RXTHRESHOLD], then IS7816[RXT] is set and an interrupt generated if

IE7816[RXTE] is set. If an error is detected due to parity or an invalid initial character,

the data is not transferred from the receive shift register to the receive buffer. Instead, the

data is overwritten by the next incoming data.

When the C7816[ISO_7816E] is set/enabled, C7816[ONACK] is set/enabled, and the

received character results in the receive buffer overflowing, a NACK is issued by the

receiver. Additionally, S1[OR] is set and an interrupt is issued if required, and the data in

the shift register is discarded.

45.4.3.4 Framing errors

If the data recovery logic does not detect a logic 1 where the stop bit should be in an

incoming frame, it sets the framing error flag, S1[FE], if S2[LBKDE] is disabled. When

S2[LBKDE] is disabled, a break character also sets the S1[FE] because a break character

Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

Freescale Semiconductor, Inc. 1115