Information

2. The address bit identifies the frame as an address character.
Note
Unless in 9-bit mode with M10 set, do not use address mark
wakeup with parity enabled.
45.4.5.3 Timing examples
Timing examples of these configurations in the NRZ mark/space data format are
illustrated in the following figures. The timing examples show all of the configurations in
the following sub-sections along with the LSB and MSB first variations.
45.4.5.3.1 Eight-bit format with parity disabled
The most significant bit can be used for address mark wakeup.
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
STOP
BIT
ADDRESS
MARK
START
BIT
START
BIT
Figure 45-204. Eight bits of data with LSB first
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
STOP
BIT
ADDRESS
MARK
START
BIT
START
BIT
Figure 45-205. Eight bits of data with MSB first
45.4.5.3.2 Eight-bit format with parity enabled
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6
STOP
BIT
START
BIT
START
BIT
PARITY
Figure 45-206. Seven bits of data with LSB first and parity
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
STOP
BIT
START
BIT
START
BIT
PARITY
Figure 45-207. Seven bits of data with MSB first and parity
45.4.5.3.3 Nine-bit format with parity disabled
The most significant bit can be used for address mark wakeup.
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
BIT 8
STOP
BIT
ADDRESS
MARK
START
BIT
START
BIT
Figure 45-208. Nine bits of data with LSB first
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1126 Freescale Semiconductor, Inc.