Information

45.4.9.2 Infrared receive decoder
The infrared receive block converts data from the RXD signal to the receive shift register.
A narrow pulse is expected for each zero received and no pulse is expected for each one
received. A narrow high pulse is expected for a zero bit when S2[RXINV] is cleared,
while a narrow low pulse is expected for a zero bit when S2[RXINV] is set. This receive
decoder meets the edge jitter requirement as defined by the IrDA serial infrared physical
layer specification.
45.5 Reset
All registers reset to a particular value are indicated in Memory map and registers.
45.6 System level interrupt sources
There are several interrupt signals that are sent from the UART. The following table lists
the interrupt sources generated by the UART. The local enables for the UART interrupt
sources are described in this table. Details regarding the individual operation of each
interrupt are contained under various sub-sections of Memory map and registers.
However, RXEDGIF description also outlines additional details regarding the RXEDGIF
interrupt because of its complexity of operation. Any of the UART interrupt requests
listed in the table can be used to bring the CPU out of Wait mode.
Table 45-210. UART interrupt sources
Interrupt Source Flag Local enable DMA select
Transmitter TDRE TIE TDMAS = 0
Transmitter TC TCIE -
Receiver IDLE ILIE -
Receiver RDRF RIE RDMAS = 0
Receiver LBKDIF LBKDIE -
Receiver RXEDGIF RXEDGIE -
Receiver OR ORIE -
Receiver NF NEIE -
Receiver FE FEIE -
Receiver PF PEIE -
Receiver RXUF RXUFE -
Transmitter TXOF TXOFE -
Table continues on the next page...
Reset
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1134 Freescale Semiconductor, Inc.