Information

Table 45-210. UART interrupt sources (continued)
Interrupt Source Flag Local enable DMA select
Receiver WT WTWE -
Receiver CWT CWTE -
Receiver BWT BWTE -
Receiver INITD INITDE -
Receiver TXT TXTE -
Receiver RXT RXTE -
Receiver GTV GTVE -
45.6.1 RXEDGIF description
S2[RXEDGIF] is set when an active edge is detected on the RxD pin. Therefore, the
active edge can be detected only when in two wire mode. A RXEDGIF interrupt is
generated only when S2[RXEDGIF] is set. If RXEDGIE is not enabled before
S2[RXEDGIF] is set, an interrupt is not generated until S2[RXEDGIF] is set.
45.6.1.1 RxD edge detect sensitivity
Edge sensitivity can be software programmed to be either falling or rising. The polarity
of the edge sensitivity is selected using S2[RXINV]. To detect the falling edge,
S2[RXINV] is programmed to 0. To detect the rising edge, S2[RXINV] is programmed
to 1.
Synchronizing logic is used prior to detect edges. Prior to detecting an edge, the receive
data on RxD input must be at the deasserted logic level. A falling edge is detected when
the RxD input signal is seen as a logic 1 (the deasserted level) during one module clock
cycle, and then a logic 0 (the asserted level) during the next cycle. A rising edge is
detected when the input is seen as a logic 0 during one module clock cycle and then a
logic 1 during the next cycle.
45.6.1.2 Clearing RXEDGIF interrupt request
Writing a logic 1 to S2[RXEDGIF] immediately clears the RXEDGIF interrupt request
even if the RxD input remains asserted. S2[RXEDGIF] remains set if another active edge
is detected on RxD while attempting to clear S2[RXEDGIF] by writing a 1 to it.
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1135