Information

45.6.1.3 Exit from low-power modes
The receive input active edge detect circuit is still active on low power modes (Wait and
Stop). An active edge on the receive input brings the CPU out of low power mode if the
interrupt is not masked (S2[RXEDGIF]=1).
45.7 DMA operation
In the transmitter, S1[TDRE] can be configured to assert a DMA transfer request. In the
receiver, S1[RDRF], can be configured to assert a DMA transfer request. The following
table shows the configuration field settings required to configure each flag for DMA
operation.
Table 45-211. DMA configuration
Flag Request enable bit DMA select bit
TDRE TIE = 1 TDMAS = 1
RDRF RIE = 1 RDMAS = 1
When a flag is configured for a DMA request, its associated DMA request is asserted
when the flag is set. When S1[RDRF] is configured as a DMA request, the clearing
mechanism of reading S1, followed by reading D, does not clear the associated flag. The
DMA request remains asserted until an indication is received that the DMA transactions
are done. When this indication is received, the flag bit and the associated DMA request is
cleared. If the DMA operation failed to remove the situation that caused the DMA
request, another request is issued.
45.8 Application information
This section describes the UART application information.
45.8.1 Transmit/receive data buffer operation
The UART has independent receive and transmit buffers. The size of these buffers may
vary depending on the implementation of the module. The implemented size of the
buffers is a fixed constant via PFIFO[TXFIFOSIZE] and PFIFO[RXFIFOSIZE].
Additionally, legacy support is provided that allows for the FIFO structure to operate as a
DMA operation
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1136 Freescale Semiconductor, Inc.