Information

In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitter
is disabled after completing the current transmit frame, and, if the Receiver Stop Enable
(RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receive
frame. Entry into Stop mode is prevented–not acknowledged–while waiting for the
transmitter and receiver to be disabled at the end of the current frame.
46.1.3.3 Low-leakage modes
When entering low-leakage modes, the Stop Enable (TCSR[STOPE] and
RCSR[STOPE]) bits are ignored and the SAI is disabled after completing the current
transmit and receive Frames. Entry into stop mode is prevented (not acknowledged)
while waiting for the transmitter and receiver to be disabled at the end of the current
frame.
46.1.3.4 Debug mode
In Debug mode, the SAI transmitter and/or receiver can continue operating provided the
Debug Enable bit is set. When TCSR[DBGE] or RCSR[DBGE] bit is clear and Debug
mode is entered, the SAI is disabled after completing the current transmit or receive
frame. The transmitter and receiver bit clocks are not affected by Debug mode.
46.2 External signals
Name Function I/O Reset Pull
SAI_TX_BCLK Transmit Bit Clock I/O 0 —
SAI_TX_SYNC Transmit Frame Sync I/O 0 —
SAI_TX_DATA Transmit Data O 0 —
SAI_RX_BCLK Receive Bit Clock I/O 0 —
SAI_RX_SYNC Receive Frame Sync I/O 0 —
SAI_RX_DATA Receive Data I 0 —
SAI_MCLK Audio Master Clock I/O 0 —
Chapter 46 Synchronous Audio Interface (SAI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1147