Information

I2Sx_RCSR field descriptions
Field Description
31
RE
Receiver Enable
Enables/disables the receiver. When software clears this field, the receiver remains enabled, and this bit
remains set, until the end of the current frame.
0 Receiver is disabled.
1 Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
30
STOPE
Stop Enable
Configures receiver operation in Stop mode. This bit is ignored and the receiver is disabled in all low-
leakage stop modes.
0 Receiver disabled in Stop mode.
1 Receiver enabled in Stop mode.
29
DBGE
Debug Enable
Enables/disables receiver operation in Debug mode. The receive bit clock is not affected by Debug mode.
0 Receiver is disabled in Debug mode, after completing the current frame.
1 Receiver is enabled in Debug mode.
28
BCE
Bit Clock Enable
Enables the receive bit clock, separately from RE. This field is automatically set whenever RE is set.
When software clears this field, the receive bit clock remains enabled, and this field remains set, until the
end of the current frame.
0 Receive bit clock is disabled.
1 Receive bit clock is enabled.
27–26
Reserved
This read-only field is reserved and always has the value zero.
25
FR
FIFO Reset
Resets the FIFO pointers. Reading this field will always return zero.
0 No effect.
1 FIFO reset.
24
SR
Software Reset
Resets the internal receiver logic including the FIFO pointers. Software-visible registers are not affected,
except for the status registers.
0 No effect.
1 Software reset.
23–21
Reserved
This read-only field is reserved and always has the value zero.
20
WSF
Word Start Flag
Indicates that the start of the configured word has been detected. Write a logic 1 to this field to clear this
flag.
Table continues on the next page...
Chapter 46 Synchronous Audio Interface (SAI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1159