Information

46.3.19 SAI MCLK Control Register (I2Sx_MCR)
The MCLK Control Register (MCR) controls the clock source and direction of the audio
master clock.
Addresses: I2S0_MCR is 4002_F000h base + 100h offset = 4002_F100h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DUF
MOE
0
MICS
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_MCR field descriptions
Field Description
31
DUF
Divider Update Flag
Provides the status of on-the-fly updates to the MCLK divider ratio.
0 MCLK divider ratio is not being updated currently.
1 MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while
this flag remains set.
30
MOE
MCLK Output Enable
Enables the MCLK divider and configures the MCLK signal pin as an output. When software clears this
field, it remains set until the MCLK divider is fully disabled.
0 MCLK signal pin is configured as an input that bypasses the MCLK divider.
1 MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.
29–26
Reserved
This read-only field is reserved and always has the value zero.
25–24
MICS
MCLK Input Clock Select
Selects the clock input to the MCLK divider. This field cannot be changed while the MCLK divider is
enabled. See the chip configuration details for information about the connections to these inputs.
00 MCLK divider input clock 0 selected.
01 MCLK divider input clock 1 selected.
10 MCLK divider input clock 2 selected.
11 MCLK divider input clock 3 selected.
23–0
Reserved
This read-only field is reserved and always has the value zero.
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1168 Freescale Semiconductor, Inc.