Information

46.4.1.1 Audio master clock
The audio master clock is used to generate the bit clock when the receiver or transmitter
is configured for an internally generated bit clock. The transmitter and receiver can
independently select between the bus clock and up to three audio master clocks to
generate the bit clock.
Each SAI peripheral can control the input clock selection, pin direction and divide ratio
of one audio master clock. The input clock selection and pin direction cannot be altered if
an SAI module using that audio master clock has been enabled. The MCLK divide ratio
can be altered while an SAI is using that master clock, although the change in the divide
ratio takes several cycles. MCR[DUF] can be polled to determine when the divide ratio
change has completed.
The audio master clock generation and selection is chip-specific. Refer to chip-specific
clocking information about how the audio master clocks are generated. A typical
implementation appears in the following figure.
Fractional
Clock
Divider
1
0
11
01
10
00
EXTAL
PLL_OUT
ALT_CLK
SYS_CLK
SAI_MOE
MCLK
MCLK_OUT
MCLK_IN
11
01
10
00
BUS_CLK
SAI_CLKMODE
Bit
Clock
Divider
1
0
BCLK_IN
SAI
BCLK_OUT
SAI_BCD
BCLK
SAI_FRACT/SAI_DIVIDE
SAI_MICS
MCLK (other SAIs)
CLKGEN
Figure 46-50. SAI master clock generation
46.4.1.2 Bit clock
The SAI transmitter and receiver support asynchronous free-running bit clocks that can
be generated internally from an audio master clock or supplied externally. There is also
the option for synchronous bit clock and frame sync operation between the receiver and
transmitter or between multiple SAI peripherals.
Externally generated bit clocks must be:
• Enabled before the SAI transmitter or receiver is enabled
• Disabled after the SAI transmitter or receiver is disabled and completes its current
frames
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1170 Freescale Semiconductor, Inc.