Information

Figure 46-52. SAI first bit shifted, MSB first
46.4.5.2 FIFO pointers
When writing to a TDR, the WFP of the corresponding TFR increments after each valid
write. The SAI supports 8-bit and 16-bit writes to TDR for transmitting 8-bit and 16-bit
data respectively.
Writes to a TDR are ignored if the corresponding bit of TCR3[TCE] is clear or if the
FIFO is full. If the Transmit FIFO is empty, the TDR must be written at least three bit
clocks before the start of the next unmasked word to avoid a FIFO underrun.
When reading an RDR, the RFP of the corresponding RFR increments after each valid
read. The SAI supports 8-bit and 16-bit reads from RDR for receiving 8-bit and 16-bit
data respectively.
Reads from an RDR are ignored if the corresponding bit of RCR3[RCE] is clear or if the
FIFO is empty. If the Receive FIFO is full, the RDR must be read at least three bit clocks
before the end of an unmasked word to avoid a FIFO overrun.
46.4.6 Word mask register
The SAI transmitter and receiver each contain a word mask register, namely TMR and
RMR, that can be used to mask any word in the frame. Because the word mask register is
double buffered, software can update it before the end of each frame to mask a particular
word in the next frame.
The TMR causes the Transmit Data pin to be tri-stated for the length of each selected
word and the transmit FIFO is not read for masked words.
Data FIFO
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1174 Freescale Semiconductor, Inc.